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| author | Richard Earnshaw <rearnsha@arm.com> | 2014-04-23 17:00:40 +0000 |
|---|---|---|
| committer | Marcus Shawcroft <mshawcroft@gcc.gnu.org> | 2014-04-23 17:00:40 +0000 |
| commit | 57b77d46b6a45f8d7ef8fd82cfddfa1aafce8cab (patch) | |
| tree | 4135fabda762dcc1f0c3060539f7b0029ec810c4 /gcc | |
| parent | 984c2f30636fcc1decc552001660b216a54c80d2 (diff) | |
| download | gcc-57b77d46b6a45f8d7ef8fd82cfddfa1aafce8cab.zip gcc-57b77d46b6a45f8d7ef8fd82cfddfa1aafce8cab.tar.gz gcc-57b77d46b6a45f8d7ef8fd82cfddfa1aafce8cab.tar.bz2 | |
[AArch64] Fully support rotate on logical operations.
From-SVN: r209711
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.c | 6 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 25 |
3 files changed, 35 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 021427b..724fa3b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2014-04-23 Richard Earnshaw <rearnsha@arm.com> + + * aarch64.md (<optab>_rol<mode>3): New pattern. + (<optab>_rolsi3_uxtw): Likewise. + * aarch64.c (aarch64_strip_shift): Handle ROTATE and ROTATERT. + 2014-04-23 James Greenhalgh <james.greenhalgh@arm.com> * config/arm/arm.c (arm_cortex_a57_tune): Initialize all fields. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 277c087..496d1b8 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -4471,9 +4471,13 @@ aarch64_strip_shift (rtx x) { rtx op = x; + /* We accept both ROTATERT and ROTATE: since the RHS must be a constant + we can convert both to ROR during final output. */ if ((GET_CODE (op) == ASHIFT || GET_CODE (op) == ASHIFTRT - || GET_CODE (op) == LSHIFTRT) + || GET_CODE (op) == LSHIFTRT + || GET_CODE (op) == ROTATERT + || GET_CODE (op) == ROTATE) && CONST_INT_P (XEXP (op, 1))) return XEXP (op, 0); diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 98c46d1..1c017e7d 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2565,7 +2565,18 @@ [(set_attr "type" "logic_shift_imm")] ) -;; zero_extend version of above +(define_insn "*<optab>_rol<mode>3" + [(set (match_operand:GPI 0 "register_operand" "=r") + (LOGICAL:GPI (rotate:GPI + (match_operand:GPI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_shift_imm_<mode>" "n")) + (match_operand:GPI 3 "register_operand" "r")))] + "" + "<logical>\\t%<w>0, %<w>3, %<w>1, ror (<sizen> - %2)" + [(set_attr "type" "logic_shift_imm")] +) + +;; zero_extend versions of above (define_insn "*<LOGICAL:optab>_<SHIFT:optab>si3_uxtw" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extend:DI @@ -2578,6 +2589,18 @@ [(set_attr "type" "logic_shift_imm")] ) +(define_insn "*<optab>_rolsi3_uxtw" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (LOGICAL:SI (rotate:SI + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "aarch64_shift_imm_si" "n")) + (match_operand:SI 3 "register_operand" "r"))))] + "" + "<logical>\\t%w0, %w3, %w1, ror (32 - %2)" + [(set_attr "type" "logic_shift_imm")] +) + (define_insn "one_cmpl<mode>2" [(set (match_operand:GPI 0 "register_operand" "=r") (not:GPI (match_operand:GPI 1 "register_operand" "r")))] |