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| author | Uros Bizjak <ubizjak@gmail.com> | 2019-09-16 20:37:28 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2019-09-16 20:37:28 +0200 |
| commit | 48d552e5cd56ff3212d050efca3d5f34778af79f (patch) | |
| tree | 03311cf5d034385e71ef869576b11ea1288ebe40 /gcc | |
| parent | e4ab9e060be99646f066264d6f23320825a46054 (diff) | |
| download | gcc-48d552e5cd56ff3212d050efca3d5f34778af79f.zip gcc-48d552e5cd56ff3212d050efca3d5f34778af79f.tar.gz gcc-48d552e5cd56ff3212d050efca3d5f34778af79f.tar.bz2 | |
re PR target/91719 (gcc compiles seq_cst store on x86-64 differently from clang/icc)
PR target/91719
* config/i386/i386.h (TARGET_USE_XCHG_FOR_ATOMIC_STORE): New macro.
* config/i386/x86-tune.def (X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE): New.
* config/i386/sync.md (atomic_store<mode>): emit XCHG for
TARGET_USE_XCHG_FOR_ATOMIC_STORE.
From-SVN: r275754
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 8 | ||||
| -rw-r--r-- | gcc/config/i386/i386.h | 2 | ||||
| -rw-r--r-- | gcc/config/i386/sync.md | 7 | ||||
| -rw-r--r-- | gcc/config/i386/x86-tune.def | 4 |
4 files changed, 19 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 63fae86..2f4de49 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,11 @@ +2019-09-16 Uroš Bizjak <ubizjak@gmail.com> + + PR target/91719 + * config/i386/i386.h (TARGET_USE_XCHG_FOR_ATOMIC_STORE): New macro. + * config/i386/x86-tune.def (X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE): New. + * config/i386/sync.md (atomic_store<mode>): emit XCHG for + TARGET_USE_XCHG_FOR_ATOMIC_STORE. + 2019-09-16 Jason Merrill <jason@redhat.com> * Makefile.in (build/genmatch.o): Depend on $(CPPLIB_H). diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index a1d0484d7..885846e 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -590,6 +590,8 @@ extern unsigned char ix86_tune_features[X86_TUNE_LAST]; ix86_tune_features[X86_TUNE_AVOID_FALSE_DEP_FOR_BMI] #define TARGET_ONE_IF_CONV_INSN \ ix86_tune_features[X86_TUNE_ONE_IF_CONV_INSN] +#define TARGET_USE_XCHG_FOR_ATOMIC_STORE \ + ix86_tune_features[X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE] #define TARGET_EMIT_VZEROUPPER \ ix86_tune_features[X86_TUNE_EMIT_VZEROUPPER] diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index ba146e3..2614ddb 100644 --- a/gcc/config/i386/sync.md +++ b/gcc/config/i386/sync.md @@ -306,8 +306,11 @@ { operands[1] = force_reg (<MODE>mode, operands[1]); - /* For seq-cst stores, when we lack MFENCE, use XCHG. */ - if (is_mm_seq_cst (model) && !(TARGET_64BIT || TARGET_SSE2)) + /* For seq-cst stores, use XCHG + when we lack MFENCE or when target prefers XCHG. */ + if (is_mm_seq_cst (model) + && (!(TARGET_64BIT || TARGET_SSE2) + || TARGET_USE_XCHG_FOR_ATOMIC_STORE)) { emit_insn (gen_atomic_exchange<mode> (gen_reg_rtx (<MODE>mode), operands[0], operands[1], diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index fd59a84..e289efd 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -313,6 +313,10 @@ DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn", m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_CORE_ALL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_GENERIC) +/* X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE: Use xchg instead of mov+mfence. */ +DEF_TUNE (X86_TUNE_USE_XCHG_FOR_ATOMIC_STORE, "use_xchg_for_atomic_store", + m_CORE_ALL | m_BDVER | m_ZNVER | m_GENERIC) + /*****************************************************************************/ /* 387 instruction selection tuning */ /*****************************************************************************/ |