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| author | David Edelsohn <edelsohn@gnu.org> | 2006-07-06 18:59:58 +0000 |
|---|---|---|
| committer | David Edelsohn <dje@gcc.gnu.org> | 2006-07-06 14:59:58 -0400 |
| commit | 429ec7dc9b70e5eebcdd7abf328e90c76b4a55bc (patch) | |
| tree | bc0244f73022f1392df38795b46228396ee7f37a /gcc | |
| parent | 1f0b926a1fe14a4ec094be7343aa7c8cf9b70716 (diff) | |
| download | gcc-429ec7dc9b70e5eebcdd7abf328e90c76b4a55bc.zip gcc-429ec7dc9b70e5eebcdd7abf328e90c76b4a55bc.tar.gz gcc-429ec7dc9b70e5eebcdd7abf328e90c76b4a55bc.tar.bz2 | |
re PR target/28150 (ICE in reload_cse_simplify_operands, at postreload.c:394)
2006-07-06 David Edelsohn <edelsohn@gnu.org>
PR target/28150
* config/rs6000/rs6000.c (rs6000_legitimate_address): Do not allow
PRE_{INC,DEC} of TFmode.
2006-07-06 David Edelsohn <edelsohn@gnu.org>
Alan Modra <amodra@bigpond.net.au>
PR target/28170
* config/rs6000/rs6000.c (insvdi_rshift_rlwimi_p): Correct shiftop
bounds. Simplify.
Co-Authored-By: Alan Modra <amodra@bigpond.net.au>
From-SVN: r115229
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/ChangeLog | 13 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 13 |
2 files changed, 20 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 53b44a7..c296175 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2006-07-06 David Edelsohn <edelsohn@gnu.org> + + PR target/28150 + * config/rs6000/rs6000.c (rs6000_legitimate_address): Do not allow + PRE_{INC,DEC} of TFmode. + +2006-07-06 David Edelsohn <edelsohn@gnu.org> + Alan Modra <amodra@bigpond.net.au> + + PR target/28170 + * config/rs6000/rs6000.c (insvdi_rshift_rlwimi_p): Correct shiftop + bounds. Simplify. + 2006-07-06 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE> PR target/28285 diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index a212611..c42bb9f 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -3522,6 +3522,7 @@ rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict) if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) && !ALTIVEC_VECTOR_MODE (mode) && !SPE_VECTOR_MODE (mode) + && mode != TFmode /* Restrict addressing for DI because of our SUBREG hackery. */ && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode)) && TARGET_UPDATE @@ -9799,12 +9800,12 @@ effects of instruction do not correspond to semantics of RTL insn. */ int insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop) { - if (INTVAL (startop) < 64 - && INTVAL (startop) > 32 - && (INTVAL (sizeop) + INTVAL (startop) < 64) - && (INTVAL (sizeop) + INTVAL (startop) > 33) - && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96) - && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64) + if (INTVAL (startop) > 32 + && INTVAL (startop) < 64 + && INTVAL (sizeop) > 1 + && INTVAL (sizeop) + INTVAL (startop) < 64 + && INTVAL (shiftop) > 0 + && INTVAL (sizeop) + INTVAL (shiftop) < 32 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop)) return 1; |