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| author | Richard Biener <rguenther@suse.de> | 2025-03-25 15:18:14 +0100 |
|---|---|---|
| committer | Richard Biener <rguenth@gcc.gnu.org> | 2025-03-26 08:25:47 +0100 |
| commit | 36925b413efb1bc3a6f068fb118205fdd391714c (patch) | |
| tree | 082be5ed169788574865465d3926552a92f97fac /gcc | |
| parent | c3a704df22f11f4d337fa5d73c642a6f7a96d6f2 (diff) | |
| download | gcc-36925b413efb1bc3a6f068fb118205fdd391714c.zip gcc-36925b413efb1bc3a6f068fb118205fdd391714c.tar.gz gcc-36925b413efb1bc3a6f068fb118205fdd391714c.tar.bz2 | |
target/119010 - add missing DF load/store reservations for znver4 and znver5
The following resolves missing reservations for DFmode *movdf_internal
loads and stores, visible as 'nothing' in -fsched-verbose=2 dumps.
PR target/119010
* config/i386/zn4zn5.md (znver4_sse_mov_fp, znver4_sse_mov_fp_load,
znver5_sse_mov_fp_load, znver4_sse_mov_fp_store,
znver5_sse_mov_fp_store): Also match V1SF and DF.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/zn4zn5.md | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/gcc/config/i386/zn4zn5.md b/gcc/config/i386/zn4zn5.md index bc7712d..954cdc5 100644 --- a/gcc/config/i386/zn4zn5.md +++ b/gcc/config/i386/zn4zn5.md @@ -1012,35 +1012,35 @@ (define_insn_reservation "znver4_sse_mov_fp" 1 (and (eq_attr "cpu" "znver4,znver5") (and (eq_attr "type" "ssemov") - (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") + (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF") (eq_attr "memory" "none")))) "znver4-direct,znver4-fpu") (define_insn_reservation "znver4_sse_mov_fp_load" 6 (and (eq_attr "cpu" "znver4") (and (eq_attr "type" "ssemov") - (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") + (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF") (eq_attr "memory" "load")))) "znver4-direct,znver4-load,znver4-fpu") (define_insn_reservation "znver5_sse_mov_fp_load" 6 (and (eq_attr "cpu" "znver5") (and (eq_attr "type" "ssemov") - (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") + (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF") (eq_attr "memory" "load")))) "znver4-direct,znver5-load,znver4-fpu") (define_insn_reservation "znver4_sse_mov_fp_store" 1 (and (eq_attr "cpu" "znver4") (and (eq_attr "type" "ssemov") - (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") + (and (eq_attr "mode" "V16SF,V8DF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF") (eq_attr "memory" "store")))) "znver4-direct,znver4-fp-store") (define_insn_reservation "znver5_sse_mov_fp_store" 1 (and (eq_attr "cpu" "znver5") (and (eq_attr "type" "ssemov") - (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,SF") + (and (eq_attr "mode" "V8SF,V4DF,V4SF,V2DF,V2SF,V1DF,DF,SF") (eq_attr "memory" "store")))) "znver4-direct,znver5-fp-store256") |