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| author | Richard Biener <rguenther@suse.de> | 2025-03-25 15:40:22 +0100 |
|---|---|---|
| committer | Richard Biener <rguenth@gcc.gnu.org> | 2025-03-26 08:23:18 +0100 |
| commit | c3a704df22f11f4d337fa5d73c642a6f7a96d6f2 (patch) | |
| tree | 9415e62423c5b1650b8e811d84dab638f4dee55a /gcc | |
| parent | 3d4bfd43059c3a92b9608d3d17f8c045a58edda1 (diff) | |
| download | gcc-c3a704df22f11f4d337fa5d73c642a6f7a96d6f2.zip gcc-c3a704df22f11f4d337fa5d73c642a6f7a96d6f2.tar.gz gcc-c3a704df22f11f4d337fa5d73c642a6f7a96d6f2.tar.bz2 | |
target/119010 - add missing integer store reservations for znver4 and znver5
The imov and imovx classified stores miss reservations in the znver4/5
pipeline description. The following adds them.
PR target/119010
* config/i386/zn4zn5.md (znver4_imov_double_store,
znver5_imov_double_store, znver4_imov_store, znver5_imov_store):
New reservations for integer stores.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/zn4zn5.md | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/gcc/config/i386/zn4zn5.md b/gcc/config/i386/zn4zn5.md index ae188a1..bc7712d 100644 --- a/gcc/config/i386/zn4zn5.md +++ b/gcc/config/i386/zn4zn5.md @@ -142,6 +142,20 @@ (eq_attr "memory" "load")))) "znver4-double,znver5-load,znver5-ieu") +(define_insn_reservation "znver4_imov_double_store" 5 + (and (eq_attr "cpu" "znver4") + (and (eq_attr "znver1_decode" "double") + (and (eq_attr "type" "imov") + (eq_attr "memory" "store")))) + "znver4-double,znver4-store,znver4-ieu") + +(define_insn_reservation "znver5_imov_double_store" 5 + (and (eq_attr "cpu" "znver5") + (and (eq_attr "znver1_decode" "double") + (and (eq_attr "type" "imov") + (eq_attr "memory" "store")))) + "znver4-double,znver5-store,znver5-ieu") + ;; imov, imovx (define_insn_reservation "znver4_imov" 1 (and (eq_attr "cpu" "znver4") @@ -167,6 +181,18 @@ (eq_attr "memory" "load"))) "znver4-direct,znver5-load,znver5-ieu") +(define_insn_reservation "znver4_imov_store" 5 + (and (eq_attr "cpu" "znver4") + (and (eq_attr "type" "imov,imovx") + (eq_attr "memory" "store"))) + "znver4-direct,znver4-store,znver4-ieu") + +(define_insn_reservation "znver5_imov_store" 5 + (and (eq_attr "cpu" "znver5") + (and (eq_attr "type" "imov,imovx") + (eq_attr "memory" "store"))) + "znver4-direct,znver5-store,znver5-ieu") + ;; Push Instruction (define_insn_reservation "znver4_push" 1 (and (eq_attr "cpu" "znver4") |