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author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2022-10-10 21:43:22 +0800 |
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committer | Kito Cheng <kito.cheng@sifive.com> | 2022-10-11 09:39:43 +0800 |
commit | 1627d05240da3b1a985b1b2006b7a9f562fe9d43 (patch) | |
tree | 8319200da42f74401f93e21aa1c24c166f2927ab /gcc | |
parent | 27bfe54e975d12aac750f0702f716a4c1c0a81fe (diff) | |
download | gcc-1627d05240da3b1a985b1b2006b7a9f562fe9d43.zip gcc-1627d05240da3b1a985b1b2006b7a9f562fe9d43.tar.gz gcc-1627d05240da3b1a985b1b2006b7a9f562fe9d43.tar.bz2 |
RISC-V: Add missing vsetvl instruction type.
When implementing built-in framework, I notice I missed
vsetvl instruction type, so add it in a single patch
preparing for the following patches.
gcc/ChangeLog:
* config/riscv/riscv.md: Add vsetvl instruction type.
Reviewed-by: Kito Cheng <kito.cheng@sifive.com>
Diffstat (limited to 'gcc')
-rw-r--r-- | gcc/config/riscv/riscv.md | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 014206f..2d1cda2 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -229,6 +229,7 @@ ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read ;; rdvl vector length vl csrr read +;; vsetvl vector configuration-setting instrucions ;; 7. Vector Loads and Stores ;; vlde vector unit-stride load instructions ;; vste vector unit-stride store instructions @@ -316,7 +317,7 @@ "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, - rdvlenb,rdvl,vlde,vste,vldm,vstm,vlds,vsts, + rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp, vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov, |