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author | Jeff Law <jlaw@ventanamicro.com> | 2024-12-30 07:40:07 -0700 |
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committer | Jeff Law <jlaw@ventanamicro.com> | 2024-12-30 07:42:54 -0700 |
commit | 64d31343d4676d8ceef9232dcd33824bc2eff330 (patch) | |
tree | b2bbd4022cd695c54826a5449d4ce6e3546a9425 /gcc/tree-ssa-phiopt.cc | |
parent | ea66f57c9603312a8e4117b719d55becbc28ec43 (diff) | |
download | gcc-64d31343d4676d8ceef9232dcd33824bc2eff330.zip gcc-64d31343d4676d8ceef9232dcd33824bc2eff330.tar.gz gcc-64d31343d4676d8ceef9232dcd33824bc2eff330.tar.bz2 |
[RISC-V][PR target/118122] Fix modes in recently added risc-v pattern
The new pattern to optimize certain code sequences on RISC-V played things a
bit fast and loose with modes -- some operands were using the ALLI iterator
while the scratch used X and the split codegen used X.
Naturally under the "right" circumstances this would trigger an ICE due to
mismatched modes. This patch uses X consistently in that pattern. It also
fixes some formatting nits.
Tested in my tester, but waiting on the pre-commit verdict before moving
forward.
PR target/118122
gcc/
* config/riscv/riscv.md (lui_constraint<X:mode>_and_to_or): Use
X iterator rather than ANYI consistently. Fix formatting.
gcc/testsuite
* gcc.target/riscv/pr118122.c: New test.
Diffstat (limited to 'gcc/tree-ssa-phiopt.cc')
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