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| author | Jeff Law <jlaw@ventanamicro.com> | 2024-12-30 07:40:07 -0700 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-12-30 07:42:54 -0700 |
| commit | 64d31343d4676d8ceef9232dcd33824bc2eff330 (patch) | |
| tree | b2bbd4022cd695c54826a5449d4ce6e3546a9425 | |
| parent | ea66f57c9603312a8e4117b719d55becbc28ec43 (diff) | |
| download | gcc-64d31343d4676d8ceef9232dcd33824bc2eff330.zip gcc-64d31343d4676d8ceef9232dcd33824bc2eff330.tar.gz gcc-64d31343d4676d8ceef9232dcd33824bc2eff330.tar.bz2 | |
[RISC-V][PR target/118122] Fix modes in recently added risc-v pattern
The new pattern to optimize certain code sequences on RISC-V played things a
bit fast and loose with modes -- some operands were using the ALLI iterator
while the scratch used X and the split codegen used X.
Naturally under the "right" circumstances this would trigger an ICE due to
mismatched modes. This patch uses X consistently in that pattern. It also
fixes some formatting nits.
Tested in my tester, but waiting on the pre-commit verdict before moving
forward.
PR target/118122
gcc/
* config/riscv/riscv.md (lui_constraint<X:mode>_and_to_or): Use
X iterator rather than ANYI consistently. Fix formatting.
gcc/testsuite
* gcc.target/riscv/pr118122.c: New test.
| -rw-r--r-- | gcc/config/riscv/riscv.md | 24 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/pr118122.c | 12 |
2 files changed, 24 insertions, 12 deletions
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 6c6155c..deb1560 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -861,19 +861,19 @@ ;; Transform (X & C1) + C2 into (X | ~C1) - (-C2 | ~C1) ;; Where C1 is not a LUI operand, but ~C1 is a LUI operand -(define_insn_and_split "*lui_constraint<ANYI:mode>_and_to_or" - [(set (match_operand:ANYI 0 "register_operand" "=r") - (plus:ANYI (and:ANYI (match_operand:ANYI 1 "register_operand" "r") - (match_operand 2 "const_int_operand")) - (match_operand 3 "const_int_operand"))) +(define_insn_and_split "*lui_constraint<X:mode>_and_to_or" + [(set (match_operand:X 0 "register_operand" "=r") + (plus:X (and:X (match_operand:X 1 "register_operand" "r") + (match_operand 2 "const_int_operand")) + (match_operand 3 "const_int_operand"))) (clobber (match_scratch:X 4 "=&r"))] - "LUI_OPERAND (~INTVAL (operands[2])) - && ((INTVAL (operands[2]) & (-INTVAL (operands[3]))) - == (-INTVAL (operands[3]))) - && riscv_const_insns (operands[3], false) - && (riscv_const_insns - (GEN_INT (~INTVAL (operands[2]) | -INTVAL (operands[3])), false) - <= riscv_const_insns (operands[3], false))" + "(LUI_OPERAND (~INTVAL (operands[2])) + && ((INTVAL (operands[2]) & (-INTVAL (operands[3]))) + == (-INTVAL (operands[3]))) + && riscv_const_insns (operands[3], false) + && (riscv_const_insns (GEN_INT (~INTVAL (operands[2]) + | -INTVAL (operands[3])), false) + <= riscv_const_insns (operands[3], false)))" "#" "&& reload_completed" [(set (match_dup 4) (match_dup 5)) diff --git a/gcc/testsuite/gcc.target/riscv/pr118122.c b/gcc/testsuite/gcc.target/riscv/pr118122.c new file mode 100644 index 0000000..0cdc3bf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr118122.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O -fno-tree-ter -fno-forward-propagate" } */ +char c; + +void +foo(short s) +{ + s += 34231u; + c = s; +} + + |