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authorPan Li <pan2.li@intel.com>2024-06-14 10:08:59 +0800
committerPan Li <pan2.li@intel.com>2024-06-14 22:07:42 +0800
commit896e043830fa4bc391db5f3cc2c33496cb8aa32e (patch)
tree00d78b9acd1cb4f393376bc981929bea20a1d800 /gcc/tree-dump.h
parent40609350e77d3fd4fac9787ff5066d723c7a6329 (diff)
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RISC-V: Add testcases for scalar unsigned SAT_SUB form 10
After the middle-end support the form 10 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 10 of unsigned .SAT_SUB. Form 10: #define SAT_SUB_U_10(T) \ T sat_sub_u_10_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return !overflow ? ret : 0; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-37.c: New test. * gcc.target/riscv/sat_u_sub-38.c: New test. * gcc.target/riscv/sat_u_sub-39.c: New test. * gcc.target/riscv/sat_u_sub-40.c: New test. * gcc.target/riscv/sat_u_sub-run-37.c: New test. * gcc.target/riscv/sat_u_sub-run-38.c: New test. * gcc.target/riscv/sat_u_sub-run-39.c: New test. * gcc.target/riscv/sat_u_sub-run-40.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
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