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authorPan Li <pan2.li@intel.com>2024-06-14 10:08:59 +0800
committerPan Li <pan2.li@intel.com>2024-06-14 22:07:42 +0800
commit896e043830fa4bc391db5f3cc2c33496cb8aa32e (patch)
tree00d78b9acd1cb4f393376bc981929bea20a1d800
parent40609350e77d3fd4fac9787ff5066d723c7a6329 (diff)
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RISC-V: Add testcases for scalar unsigned SAT_SUB form 10
After the middle-end support the form 10 of unsigned SAT_SUB and the RISC-V backend implement the scalar .SAT_SUB, add more test case to cover the form 10 of unsigned .SAT_SUB. Form 10: #define SAT_SUB_U_10(T) \ T sat_sub_u_10_##T (T x, T y) \ { \ T ret; \ T overflow = __builtin_sub_overflow (x, y, &ret); \ return !overflow ? ret : 0; \ } Passed the rv64gcv fully regression test. gcc/testsuite/ChangeLog: * gcc.target/riscv/sat_arith.h: Add helper macro for test. * gcc.target/riscv/sat_u_sub-37.c: New test. * gcc.target/riscv/sat_u_sub-38.c: New test. * gcc.target/riscv/sat_u_sub-39.c: New test. * gcc.target/riscv/sat_u_sub-40.c: New test. * gcc.target/riscv/sat_u_sub-run-37.c: New test. * gcc.target/riscv/sat_u_sub-run-38.c: New test. * gcc.target/riscv/sat_u_sub-run-39.c: New test. * gcc.target/riscv/sat_u_sub-run-40.c: New test. Signed-off-by: Pan Li <pan2.li@intel.com>
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_arith.h10
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c18
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c19
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c18
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c17
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c25
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c25
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c25
-rw-r--r--gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c25
9 files changed, 182 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/sat_arith.h b/gcc/testsuite/gcc.target/riscv/sat_arith.h
index ecb74e5..4c02783 100644
--- a/gcc/testsuite/gcc.target/riscv/sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/sat_arith.h
@@ -147,6 +147,15 @@ sat_u_sub_##T##_fmt_9 (T x, T y) \
return overflow ? 0 : ret; \
}
+#define DEF_SAT_U_SUB_FMT_10(T) \
+T __attribute__((noinline)) \
+sat_u_sub_##T##_fmt_10 (T x, T y) \
+{ \
+ T ret; \
+ T overflow = __builtin_sub_overflow (x, y, &ret); \
+ return !overflow ? ret : 0; \
+}
+
#define RUN_SAT_U_SUB_FMT_1(T, x, y) sat_u_sub_##T##_fmt_1(x, y)
#define RUN_SAT_U_SUB_FMT_2(T, x, y) sat_u_sub_##T##_fmt_2(x, y)
#define RUN_SAT_U_SUB_FMT_3(T, x, y) sat_u_sub_##T##_fmt_3(x, y)
@@ -156,6 +165,7 @@ sat_u_sub_##T##_fmt_9 (T x, T y) \
#define RUN_SAT_U_SUB_FMT_7(T, x, y) sat_u_sub_##T##_fmt_7(x, y)
#define RUN_SAT_U_SUB_FMT_8(T, x, y) sat_u_sub_##T##_fmt_8(x, y)
#define RUN_SAT_U_SUB_FMT_9(T, x, y) sat_u_sub_##T##_fmt_9(x, y)
+#define RUN_SAT_U_SUB_FMT_10(T, x, y) sat_u_sub_##T##_fmt_10(x, y)
#define DEF_VEC_SAT_U_SUB_FMT_1(T) \
void __attribute__((noinline)) \
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c
new file mode 100644
index 0000000..8c97a51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-37.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint8_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*[atx][0-9]+,\s*[atx][0-9]+
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*a0,\s*[atx][0-9]+
+** andi\s+a0,\s*a0,\s*0xff
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint8_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c
new file mode 100644
index 0000000..7e3cec2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-38.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint16_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** slli\s+a0,\s*a0,\s*48
+** srli\s+a0,\s*a0,\s*48
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint16_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c
new file mode 100644
index 0000000..cd37f52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-39.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint32_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+[atx][0-9]+,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** sext.w\s+a0,\s*a0
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint32_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c
new file mode 100644
index 0000000..165be89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-40.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -O3 -fdump-rtl-expand-details -fno-schedule-insns -fno-schedule-insns2" } */
+/* { dg-final { check-function-bodies "**" "" } } */
+
+#include "sat_arith.h"
+
+/*
+** sat_u_sub_uint64_t_fmt_10:
+** sub\s+[atx][0-9]+,\s*a0,\s*a1
+** sltu\s+[atx][0-9]+,\s*a0,\s*a1
+** addi\s+a0,\s*[atx][0-9]+,\s*-1
+** and\s+a0,\s*[atx][0-9]+,\s*[atx][0-9]+
+** ret
+*/
+DEF_SAT_U_SUB_FMT_10(uint64_t)
+
+/* { dg-final { scan-rtl-dump-times ".SAT_SUB " 2 "expand" } } */
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c
new file mode 100644
index 0000000..2a157f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-37.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint8_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 255, 254, 1, },
+ { 255, 255, 0, },
+ { 254, 255, 0, },
+ { 253, 254, 0, },
+ { 0, 255, 0, },
+ { 1, 255, 0, },
+ { 32, 5, 27, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c
new file mode 100644
index 0000000..ae87544
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-38.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint16_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 65535, 65534, 1, },
+ { 65535, 65535, 0, },
+ { 65534, 65535, 0, },
+ { 65533, 65534, 0, },
+ { 0, 65535, 0, },
+ { 1, 65535, 0, },
+ { 35, 5, 30, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c
new file mode 100644
index 0000000..43414ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-39.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint32_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 4294967295, 4294967294, 1, },
+ { 4294967295, 4294967295, 0, },
+ { 4294967294, 4294967295, 0, },
+ { 4294967293, 4294967294, 0, },
+ { 1, 4294967295, 0, },
+ { 2, 4294967295, 0, },
+ { 5, 1, 4, },
+};
+
+#include "scalar_sat_binary.h"
diff --git a/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c
new file mode 100644
index 0000000..3ef70a1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/sat_u_sub-run-40.c
@@ -0,0 +1,25 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "sat_arith.h"
+
+#define T uint64_t
+#define RUN_SAT_BINARY RUN_SAT_U_SUB_FMT_10
+
+DEF_SAT_U_SUB_FMT_10(T)
+
+T test_data[][3] = {
+ /* arg_0, arg_1, expect */
+ { 0, 0, 0, },
+ { 0, 1, 0, },
+ { 1, 1, 0, },
+ { 18446744073709551615u, 18446744073709551614u, 1, },
+ { 18446744073709551615u, 18446744073709551615u, 0, },
+ { 18446744073709551614u, 18446744073709551615u, 0, },
+ { 18446744073709551613u, 18446744073709551614u, 0, },
+ { 0, 18446744073709551615u, 0, },
+ { 1, 18446744073709551615u, 0, },
+ { 43, 11, 32, },
+};
+
+#include "scalar_sat_binary.h"