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| author | Jeff Law <jlaw@ventanamicro.com> | 2024-06-15 21:17:10 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-06-15 21:18:43 -0600 |
| commit | 0240909cb03f2a37a74364b00e51ad782c748551 (patch) | |
| tree | 34bf4c33f70866dc4835bc07797b7e000563e64a /gcc/tree-dump.h | |
| parent | bc630d613db94eb50687a009ae6b45098ab02db5 (diff) | |
| download | gcc-0240909cb03f2a37a74364b00e51ad782c748551.zip gcc-0240909cb03f2a37a74364b00e51ad782c748551.tar.gz gcc-0240909cb03f2a37a74364b00e51ad782c748551.tar.bz2 | |
[committed] Fix minor SH scan-asm failure after recent IOR->ADD changes
This fixes minor fallout from the IOR->ADD change for rotates that I installed
a little while ago.
Basically the SH backend has a special pattern for setting the T register that
has elements similar to a rotate. With the IOR->ADD change that pattern no
longer matches and we get scan-asm failures.
Fixing isn't a trivial case of just replacing IOR with ADD as the IOR->ADD
change changes some of the simplifications/canonicalizations along the way.
The net is we need a pattern with a slightly different structure. I've
regression tested this on sh3[eb]-linux-gnu and bootstrapped sh4-linux-gnu
(without a regression test).
gcc/
* config/sh/sh.md (neg_zero_extract_4b): New pattern.
Diffstat (limited to 'gcc/tree-dump.h')
0 files changed, 0 insertions, 0 deletions