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| author | Jeff Law <jlaw@ventanamicro.com> | 2024-06-15 21:17:10 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-06-15 21:18:43 -0600 |
| commit | 0240909cb03f2a37a74364b00e51ad782c748551 (patch) | |
| tree | 34bf4c33f70866dc4835bc07797b7e000563e64a /gcc | |
| parent | bc630d613db94eb50687a009ae6b45098ab02db5 (diff) | |
| download | gcc-0240909cb03f2a37a74364b00e51ad782c748551.zip gcc-0240909cb03f2a37a74364b00e51ad782c748551.tar.gz gcc-0240909cb03f2a37a74364b00e51ad782c748551.tar.bz2 | |
[committed] Fix minor SH scan-asm failure after recent IOR->ADD changes
This fixes minor fallout from the IOR->ADD change for rotates that I installed
a little while ago.
Basically the SH backend has a special pattern for setting the T register that
has elements similar to a rotate. With the IOR->ADD change that pattern no
longer matches and we get scan-asm failures.
Fixing isn't a trivial case of just replacing IOR with ADD as the IOR->ADD
change changes some of the simplifications/canonicalizations along the way.
The net is we need a pattern with a slightly different structure. I've
regression tested this on sh3[eb]-linux-gnu and bootstrapped sh4-linux-gnu
(without a regression test).
gcc/
* config/sh/sh.md (neg_zero_extract_4b): New pattern.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/sh/sh.md | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 19481c0..92a1efe 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -10093,6 +10093,25 @@ [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 1) (match_dup 2)))]) +;; Same thing, but when we use a PLUS rather than IOR/XOR for the rotation +;; which causes things to simplify somewhat differently. +(define_insn_and_split "*neg_zero_extract_4b" + [(set (reg:SI T_REG) + (and:SI (not:SI (plus:SI + (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand") + (match_operand 1 "const_int_operand")) + (ashift:SI (match_operand:SI 2 "arith_reg_operand") + (match_operand 3 "const_int_operand")))) + (const_int 1)))] + "TARGET_SH1 && can_create_pseudo_p () + && INTVAL (operands[3]) > 0 + && INTVAL (operands[1]) + INTVAL (operands[3]) == 32" + "#" + "&& 1" + [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (match_dup 4)) + (const_int 1) (match_dup 1)))] + { operands[4] = GEN_INT (1 << INTVAL (operands[1])); }) + (define_insn_and_split "*neg_zero_extract_5" [(set (reg:SI T_REG) (and:SI (not:SI (subreg:SI |