diff options
| author | Pan Li <pan2.li@intel.com> | 2023-05-15 22:05:44 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-05-15 22:05:44 +0800 |
| commit | 47c4e96ad61a19ec3adb39587bf0d7d0b51a51b3 (patch) | |
| tree | 9fad808aaf88f2535c4423f8b52f693220cac32b /gcc/tree-data-ref.cc | |
| parent | 30adfb85ff994c0faa0cc556ba46838b218263f5 (diff) | |
| download | gcc-47c4e96ad61a19ec3adb39587bf0d7d0b51a51b3.zip gcc-47c4e96ad61a19ec3adb39587bf0d7d0b51a51b3.tar.gz gcc-47c4e96ad61a19ec3adb39587bf0d7d0b51a51b3.tar.bz2 | |
OPTABS: Extend the number of expanding instructions pattern
We (RVV) is going to add a rounding mode operand into floating-point
instructions which have 11 operands.
Since we are going have intrinsic that is adding rounding mode argument:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
This is the patch that is adding rounding mode operand in RISC-V port:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618573.html
You can see there are 11 operands in these patterns.
gcc/ChangeLog:
* optabs.cc (maybe_gen_insn): Add case to generate instruction
that has 11 operands.
Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
Diffstat (limited to 'gcc/tree-data-ref.cc')
0 files changed, 0 insertions, 0 deletions