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| author | Pan Li <pan2.li@intel.com> | 2023-05-15 22:05:44 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-05-15 22:05:44 +0800 |
| commit | 47c4e96ad61a19ec3adb39587bf0d7d0b51a51b3 (patch) | |
| tree | 9fad808aaf88f2535c4423f8b52f693220cac32b | |
| parent | 30adfb85ff994c0faa0cc556ba46838b218263f5 (diff) | |
| download | gcc-47c4e96ad61a19ec3adb39587bf0d7d0b51a51b3.zip gcc-47c4e96ad61a19ec3adb39587bf0d7d0b51a51b3.tar.gz gcc-47c4e96ad61a19ec3adb39587bf0d7d0b51a51b3.tar.bz2 | |
OPTABS: Extend the number of expanding instructions pattern
We (RVV) is going to add a rounding mode operand into floating-point
instructions which have 11 operands.
Since we are going have intrinsic that is adding rounding mode argument:
https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/226
This is the patch that is adding rounding mode operand in RISC-V port:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618573.html
You can see there are 11 operands in these patterns.
gcc/ChangeLog:
* optabs.cc (maybe_gen_insn): Add case to generate instruction
that has 11 operands.
Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
| -rw-r--r-- | gcc/optabs.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gcc/optabs.cc b/gcc/optabs.cc index c8e39c8..a12333c 100644 --- a/gcc/optabs.cc +++ b/gcc/optabs.cc @@ -8139,6 +8139,11 @@ maybe_gen_insn (enum insn_code icode, unsigned int nops, ops[3].value, ops[4].value, ops[5].value, ops[6].value, ops[7].value, ops[8].value, ops[9].value); + case 11: + return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, + ops[3].value, ops[4].value, ops[5].value, + ops[6].value, ops[7].value, ops[8].value, + ops[9].value, ops[10].value); } gcc_unreachable (); } |