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| author | Robin Dapp <rdapp@ventanamicro.com> | 2024-09-26 11:56:08 +0200 |
|---|---|---|
| committer | Robin Dapp <rdapp@ventanamicro.com> | 2024-11-19 12:23:12 +0100 |
| commit | a18592e1c30f0f539c71fa632c49cb82008ec45a (patch) | |
| tree | abf6f2a6646e1b2e1ef14d4d68d906213a50dbcc /gcc/testsuite | |
| parent | 387dba05e4207fc3f9a2f2bcb09a343a999c76fc (diff) | |
| download | gcc-a18592e1c30f0f539c71fa632c49cb82008ec45a.zip gcc-a18592e1c30f0f539c71fa632c49cb82008ec45a.tar.gz gcc-a18592e1c30f0f539c71fa632c49cb82008ec45a.tar.bz2 | |
RISC-V: Load VLS perm indices directly from memory.
Instead of loading the permutation indices and using vmslt in order to
determine which elements belong to which source vector we can compute
the proper mask at compile time. That way we can emit vlm instead of
vle + vmslt.
gcc/ChangeLog:
* config/riscv/riscv-v.cc (shuffle_merge_patterns): Load VLS
indices directly.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/merge-1.c: Check for vlm and
no vmsleu etc.
* gcc.target/riscv/rvv/autovec/vls/merge-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/merge-3.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/merge-4.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/merge-5.c: Ditto.
* gcc.target/riscv/rvv/autovec/vls/merge-6.c: Ditto.
Diffstat (limited to 'gcc/testsuite')
6 files changed, 12 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c index cd24922..c34734c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c @@ -4,3 +4,5 @@ #include "../vls-vlmax/merge-1.c" /* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */ +/* { dg-final { scan-assembler-not {\tvms} } } */ +/* { dg-final { scan-assembler-times {\tvlm.v} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c index 52d9124..68f7b62 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c @@ -4,3 +4,5 @@ #include "../vls-vlmax/merge-2.c" /* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */ +/* { dg-final { scan-assembler-not {\tvms} } } */ +/* { dg-final { scan-assembler-times {\tvlm.v} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c index 4931d2a..1250dca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c @@ -4,3 +4,5 @@ #include "../vls-vlmax/merge-3.c" /* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */ +/* { dg-final { scan-assembler-not {\tvms} } } */ +/* { dg-final { scan-assembler-times {\tvlm.v} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c index f22a18f..1dfd828 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c @@ -4,3 +4,5 @@ #include "../vls-vlmax/merge-4.c" /* dg-final scan-assembler-times {\tvmerge.vvm} 11 */ +/* { dg-final { scan-assembler-not {\tvms} } } */ +/* { dg-final { scan-assembler-times {\tvlm.v} 11 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c index cf8d04c..af84a65 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c @@ -4,3 +4,5 @@ #include "../vls-vlmax/merge-5.c" /* { dg-final { scan-assembler-times {\tvmerge.vvm} 8 } } */ +/* { dg-final { scan-assembler-not {\tvms} } } */ +/* { dg-final { scan-assembler-times {\tvlm.v} 8 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c index 3b6f977..45e9998 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c @@ -4,3 +4,5 @@ #include "../vls-vlmax/merge-6.c" /* { dg-final { scan-assembler-times {\tvmerge.vvm} 5 } } */ +/* { dg-final { scan-assembler-not {\tvms} } } */ +/* { dg-final { scan-assembler-times {\tvlm.v} 5 } } */ |