From a18592e1c30f0f539c71fa632c49cb82008ec45a Mon Sep 17 00:00:00 2001
From: Robin Dapp <rdapp@ventanamicro.com>
Date: Thu, 26 Sep 2024 11:56:08 +0200
Subject: RISC-V: Load VLS perm indices directly from memory.

Instead of loading the permutation indices and using vmslt in order to
determine which elements belong to which source vector we can compute
the proper mask at compile time.  That way we can emit vlm instead of
vle + vmslt.

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (shuffle_merge_patterns): Load VLS
	indices directly.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/vls/merge-1.c: Check for vlm and
	no vmsleu etc.
	* gcc.target/riscv/rvv/autovec/vls/merge-2.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/merge-3.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/merge-4.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/merge-5.c: Ditto.
	* gcc.target/riscv/rvv/autovec/vls/merge-6.c: Ditto.
---
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c | 2 ++
 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c | 2 ++
 6 files changed, 12 insertions(+)

(limited to 'gcc/testsuite')

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c
index cd24922..c34734c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-1.c
@@ -4,3 +4,5 @@
 #include "../vls-vlmax/merge-1.c"
 
 /* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */
+/* { dg-final { scan-assembler-not {\tvms} } } */
+/* { dg-final { scan-assembler-times {\tvlm.v} 11 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c
index 52d9124..68f7b62 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-2.c
@@ -4,3 +4,5 @@
 #include "../vls-vlmax/merge-2.c"
 
 /* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */
+/* { dg-final { scan-assembler-not {\tvms} } } */
+/* { dg-final { scan-assembler-times {\tvlm.v} 11 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c
index 4931d2a..1250dca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-3.c
@@ -4,3 +4,5 @@
 #include "../vls-vlmax/merge-3.c"
 
 /* { dg-final { scan-assembler-times {\tvmerge.vvm} 11 } } */
+/* { dg-final { scan-assembler-not {\tvms} } } */
+/* { dg-final { scan-assembler-times {\tvlm.v} 11 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
index f22a18f..1dfd828 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-4.c
@@ -4,3 +4,5 @@
 #include "../vls-vlmax/merge-4.c"
 
 /* dg-final scan-assembler-times {\tvmerge.vvm} 11 */
+/* { dg-final { scan-assembler-not {\tvms} } } */
+/* { dg-final { scan-assembler-times {\tvlm.v} 11 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c
index cf8d04c..af84a65 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-5.c
@@ -4,3 +4,5 @@
 #include "../vls-vlmax/merge-5.c"
 
 /* { dg-final { scan-assembler-times {\tvmerge.vvm} 8 } } */
+/* { dg-final { scan-assembler-not {\tvms} } } */
+/* { dg-final { scan-assembler-times {\tvlm.v} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c
index 3b6f977..45e9998 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/merge-6.c
@@ -4,3 +4,5 @@
 #include "../vls-vlmax/merge-6.c"
 
 /* { dg-final { scan-assembler-times {\tvmerge.vvm} 5 } } */
+/* { dg-final { scan-assembler-not {\tvms} } } */
+/* { dg-final { scan-assembler-times {\tvlm.v} 5 } } */
-- 
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