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authorliuhongt <hongtao.liu@intel.com>2021-08-23 17:00:36 +0800
committerliuhongt <hongtao.liu@intel.com>2021-08-23 17:52:03 +0800
commit70c7ab5c487f392e04907ce8f22eb454b8d3c4ff (patch)
treee5370efbcfbfbcd074ba4e1a37208f38e4819fe5 /gcc/testsuite
parentb284053bb75661fc1bf13c275f3ba5364bb17608 (diff)
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Fix ICE.
gcc/ChangeLog: PR target/102016 * config/i386/sse.md (*avx512f_pshufb_truncv8hiv8qi_1): Add TARGET_AVX512BW to condition. gcc/testsuite/ChangeLog: PR target/102016 * gcc.target/i386/pr102016.c: New test.
Diffstat (limited to 'gcc/testsuite')
-rw-r--r--gcc/testsuite/gcc.target/i386/pr102016.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/gcc/testsuite/gcc.target/i386/pr102016.c b/gcc/testsuite/gcc.target/i386/pr102016.c
new file mode 100644
index 0000000..2ff75cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr102016.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+typedef char v8qi __attribute__((vector_size (8)));
+typedef char v16qi __attribute__((vector_size (16)));
+v8qi
+foo_wb_128 (v16qi x)
+{
+ return __builtin_shufflevector (x, x,
+ 0, 2, 4, 6, 8, 10, 12, 14);
+}