From 70c7ab5c487f392e04907ce8f22eb454b8d3c4ff Mon Sep 17 00:00:00 2001 From: liuhongt Date: Mon, 23 Aug 2021 17:00:36 +0800 Subject: Fix ICE. gcc/ChangeLog: PR target/102016 * config/i386/sse.md (*avx512f_pshufb_truncv8hiv8qi_1): Add TARGET_AVX512BW to condition. gcc/testsuite/ChangeLog: PR target/102016 * gcc.target/i386/pr102016.c: New test. --- gcc/testsuite/gcc.target/i386/pr102016.c | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr102016.c (limited to 'gcc/testsuite') diff --git a/gcc/testsuite/gcc.target/i386/pr102016.c b/gcc/testsuite/gcc.target/i386/pr102016.c new file mode 100644 index 0000000..2ff75cb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr102016.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -O2" } */ +typedef char v8qi __attribute__((vector_size (8))); +typedef char v16qi __attribute__((vector_size (16))); +v8qi +foo_wb_128 (v16qi x) +{ + return __builtin_shufflevector (x, x, + 0, 2, 4, 6, 8, 10, 12, 14); +} -- cgit v1.1