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| author | Hu, Lin1 <lin1.hu@intel.com> | 2025-03-26 16:15:52 +0800 |
|---|---|---|
| committer | Hu, Lin1 <lin1.hu@intel.com> | 2025-04-01 09:50:23 +0800 |
| commit | e5cfa7f797b79613e5483786484567b9ca72db06 (patch) | |
| tree | 294d13c044007456f165f7ba68277be123b8db75 /gcc/testsuite/rust/compile/for-loop1.rs | |
| parent | 28751389a68e131e21fcaf8e3f661d76a2b4d0cc (diff) | |
| download | gcc-e5cfa7f797b79613e5483786484567b9ca72db06.zip gcc-e5cfa7f797b79613e5483786484567b9ca72db06.tar.gz gcc-e5cfa7f797b79613e5483786484567b9ca72db06.tar.bz2 | |
i386: Add attr_isa for vaes patterns to sync with attr gpr16. [pr119473]
For vaes patterns with jm constraint and gpr16 attr, it requires "isa"
attr to distinct avx/avx512 alternatives in ix86_memory_address_reg_class.
Also adds missing type and mode attributes for those vaes patterns.
gcc/ChangeLog:
PR target/119473
* config/i386/sse.md
(vaesdec_<mode>): Set attr "isa" as "avx,vaes_avx512vl", "type" as
"sselog1", "mode" as "TI".
(vaesdeclast_<mode>): Ditto.
(vaesenc_<mode>): Ditto.
(vaesenclast_<mode>): Ditto.
gcc/testsuite/ChangeLog:
PR target/119473
* gcc.target/i386/pr119473.c: New test.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Diffstat (limited to 'gcc/testsuite/rust/compile/for-loop1.rs')
0 files changed, 0 insertions, 0 deletions