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| author | Hu, Lin1 <lin1.hu@intel.com> | 2025-03-26 16:15:52 +0800 |
|---|---|---|
| committer | Hu, Lin1 <lin1.hu@intel.com> | 2025-04-01 09:50:23 +0800 |
| commit | e5cfa7f797b79613e5483786484567b9ca72db06 (patch) | |
| tree | 294d13c044007456f165f7ba68277be123b8db75 /gcc | |
| parent | 28751389a68e131e21fcaf8e3f661d76a2b4d0cc (diff) | |
| download | gcc-e5cfa7f797b79613e5483786484567b9ca72db06.zip gcc-e5cfa7f797b79613e5483786484567b9ca72db06.tar.gz gcc-e5cfa7f797b79613e5483786484567b9ca72db06.tar.bz2 | |
i386: Add attr_isa for vaes patterns to sync with attr gpr16. [pr119473]
For vaes patterns with jm constraint and gpr16 attr, it requires "isa"
attr to distinct avx/avx512 alternatives in ix86_memory_address_reg_class.
Also adds missing type and mode attributes for those vaes patterns.
gcc/ChangeLog:
PR target/119473
* config/i386/sse.md
(vaesdec_<mode>): Set attr "isa" as "avx,vaes_avx512vl", "type" as
"sselog1", "mode" as "TI".
(vaesdeclast_<mode>): Ditto.
(vaesenc_<mode>): Ditto.
(vaesenclast_<mode>): Ditto.
gcc/testsuite/ChangeLog:
PR target/119473
* gcc.target/i386/pr119473.c: New test.
Co-authored-by: Hongyu Wang <hongyu.wang@intel.com>
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/i386/sse.md | 20 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr119473.c | 26 |
2 files changed, 42 insertions, 4 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 92dc93c..b280676 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -30849,7 +30849,10 @@ else return "vaesdec\t{%2, %1, %0|%0, %1, %2}"; } -[(set_attr "addr" "gpr16,*")]) +[(set_attr "isa" "avx,vaes_avx512vl") + (set_attr "type" "sselog1") + (set_attr "addr" "gpr16,*") + (set_attr "mode" "TI")]) (define_insn "vaesdeclast_<mode>" [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v") @@ -30864,7 +30867,10 @@ else return "vaesdeclast\t{%2, %1, %0|%0, %1, %2}"; } -[(set_attr "addr" "gpr16,*")]) +[(set_attr "isa" "avx,vaes_avx512vl") + (set_attr "type" "sselog1") + (set_attr "addr" "gpr16,*") + (set_attr "mode" "TI")]) (define_insn "vaesenc_<mode>" [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v") @@ -30879,7 +30885,10 @@ else return "vaesenc\t{%2, %1, %0|%0, %1, %2}"; } -[(set_attr "addr" "gpr16,*")]) +[(set_attr "isa" "avx,vaes_avx512vl") + (set_attr "type" "sselog1") + (set_attr "addr" "gpr16,*") + (set_attr "mode" "TI")]) (define_insn "vaesenclast_<mode>" [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=x,v") @@ -30894,7 +30903,10 @@ else return "vaesenclast\t{%2, %1, %0|%0, %1, %2}"; } -[(set_attr "addr" "gpr16,*")]) +[(set_attr "isa" "avx,vaes_avx512vl") + (set_attr "type" "sselog1") + (set_attr "addr" "gpr16,*") + (set_attr "mode" "TI")]) (define_insn "vpclmulqdq_<mode>" [(set (match_operand:VI8_FVL 0 "register_operand" "=v") diff --git a/gcc/testsuite/gcc.target/i386/pr119473.c b/gcc/testsuite/gcc.target/i386/pr119473.c new file mode 100644 index 0000000..574c921 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr119473.c @@ -0,0 +1,26 @@ +/* PR target/119473 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mapxf -m64 -mvaes" } */ + +typedef char __v32qi __attribute__ ((__vector_size__(32))); +typedef long long __m256i __attribute__((__vector_size__(32), __aligned__(32))); + +typedef union +{ + __v32qi qi[8]; +} tmp_u; + + +void foo () +{ + register tmp_u *tdst __asm__("%rdx"); + register tmp_u *src1 __asm__("%rcx"); + register tmp_u *src2 __asm__("%r26"); + + tdst->qi[0] = __builtin_ia32_vaesdec_v32qi(src1->qi[0], src2->qi[0]); + tdst->qi[0] = __builtin_ia32_vaesdeclast_v32qi(src1->qi[0], src2->qi[0]); + tdst->qi[0] = __builtin_ia32_vaesenc_v32qi(src1->qi[0], src2->qi[0]); + tdst->qi[0] = __builtin_ia32_vaesenclast_v32qi(src1->qi[0], src2->qi[0]); +} + +/* { dg-final { scan-assembler-not "\\\(%r26\\\), " } } */ |