re PR target/16176 (Miscompilation of unaligned data in MIPS backend (SB1 flavor))

	PR target/16176
	* config/mips/mips.c (mips_expand_unaligned_load): Use a temporary
	register for the destination of the lwl or ldl.

From-SVN: r83668

1 files changed, 20 insertions, 0 deletions

diff --git a/gcc/testsuite/gcc.c-torture/execute/20040625-1.c b/gcc/testsuite/gcc.c-torture/execute/20040625-1.c
new file mode 100644
index 0000000..c426055
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/execute/20040625-1.c
@@ -0,0 +1,20 @@
+/* From PR target/16176 */
+struct __attribute__ ((packed)) s { struct s *next; };
+
+struct s * __attribute__ ((noinline))
+maybe_next (struct s *s, int t)
+{
+  if (t)
+    s = s->next;
+  return s;
+}
+
+int main ()
+{
+  struct s s1, s2;
+
+  s1.next = &s2;
+  if (maybe_next (&s1, 1) != &s2)
+    abort ();
+  exit (0);
+}