From f1526aaae77c8082ef42691d03254926f5104b64 Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Fri, 25 Jun 2004 18:24:51 +0000 Subject: re PR target/16176 (Miscompilation of unaligned data in MIPS backend (SB1 flavor)) PR target/16176 * config/mips/mips.c (mips_expand_unaligned_load): Use a temporary register for the destination of the lwl or ldl. From-SVN: r83668 --- gcc/testsuite/gcc.c-torture/execute/20040625-1.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 gcc/testsuite/gcc.c-torture/execute/20040625-1.c (limited to 'gcc/testsuite/gcc.c-torture') diff --git a/gcc/testsuite/gcc.c-torture/execute/20040625-1.c b/gcc/testsuite/gcc.c-torture/execute/20040625-1.c new file mode 100644 index 0000000..c426055 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/20040625-1.c @@ -0,0 +1,20 @@ +/* From PR target/16176 */ +struct __attribute__ ((packed)) s { struct s *next; }; + +struct s * __attribute__ ((noinline)) +maybe_next (struct s *s, int t) +{ + if (t) + s = s->next; + return s; +} + +int main () +{ + struct s s1, s2; + + s1.next = &s2; + if (maybe_next (&s1, 1) != &s2) + abort (); + exit (0); +} -- cgit v1.1