diff options
| author | Pan Li <pan2.li@intel.com> | 2024-11-21 14:30:46 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-11-24 15:49:11 +0800 |
| commit | 847b4b0ef473a37f9a6793da7c9af96928463e97 (patch) | |
| tree | 32e97b7e7fa38abd66e4a5dc5510ab0067f10ba8 /gcc/function.cc | |
| parent | 4abd0af79f88e671153cec6f0532489f2672c07d (diff) | |
| download | gcc-847b4b0ef473a37f9a6793da7c9af96928463e97.zip gcc-847b4b0ef473a37f9a6793da7c9af96928463e97.tar.gz gcc-847b4b0ef473a37f9a6793da7c9af96928463e97.tar.bz2 | |
RISC-V: Refactor the testcases for vector SAT_TRUNC
This patch would like to refactor the testcases of vector SAT_TRUNC
after move to rvv/autovec/sat folder. Includes:
* Refine the include header files.
* Remove unnecessary optimization options.
The below test suites are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c:
Refine the include file and remove unnecessary optimization options.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c: Ditto
* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c: Ditto
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/function.cc')
0 files changed, 0 insertions, 0 deletions