RISC-V: Refactor the testcases for vector SAT_TRUNC

This patch would like to refactor the testcases of vector SAT_TRUNC
after move to rvv/autovec/sat folder.  Includes:

* Refine the include header files.
* Remove unnecessary optimization options.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c:
	Refine the include file and remove unnecessary optimization options.
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c: Ditto

Signed-off-by: Pan Li <pan2.li@intel.com>

48 files changed, 72 insertions, 72 deletions

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c
index 5354717..bf83a5c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint32_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c
index 15654b4..0102249 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c
index 1e272ae..4f3efb9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint32_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c
index 3d29d26..118a726 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-1-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint8_t, uint16_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c
index fc43a8a..8c1f3ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint32_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c
index b5a3fc3..400f892 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint16_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c
index 9ed21e2..184a5fe 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint32_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c
index eb7d961..70a096e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-2-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_1 (uint16_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c
index c9634d38..b4365bd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint32_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c
index d2239d3..614a189 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint16_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c
index 9c671cb..7e00068 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint32_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c
index d93453f..1e9a584 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-3-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_2 (uint8_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c
index 072d189..59acd8b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint32_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c
index 837551c..70563d6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c
index 3174f45..bfc504e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint32_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c
index 04d1204..5685734 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-4-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint8_t, uint16_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c
index 32a30f3..a615cfa 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint32_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c
index dd14fad..457cc37 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint16_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c
index b77fcd4..c4a09b2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint32_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c
index f177f7b..e19ea9b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-5-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_3 (uint16_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c
index 8b27b69..772924f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint32_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c
index df1752c..a4b1895 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint16_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c
index 200c559..d8c33c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint32_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c
index db788e1..25f6665 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-6-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fdump-rtl-expand-details" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize -fdump-rtl-expand-details" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 
 DEF_VEC_SAT_U_TRUNC_FMT_4 (uint8_t, uint64_t)
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c
index a51ad60..227a052 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c
index 90a12c9..0fb8103 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c
index 3e7a7ed..7d69afc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c
index 4e387d8..dddc652 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-1-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c
index 82396f5..7ab7399 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c
index 33eea81..cf0a79a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c
index d804b85..f0de859 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c
index ffb9e6f..a5e822c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-2-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c
index e7852dd..a0557be 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c
index 283fb64..6a535de 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c
index 8b00555..9fac144 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c
index c580fda..e084ff7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-3-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c
index 499eb17..b2e812d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c
index b42ad62..9190c71 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c
index 662b33a..3d26721 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c
index 1247ea3..3ea1669 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-4-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c
index 2a47a8e..0517aad 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c
index 4e387d8..dddc652 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c
index a51ad60..227a052 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c
index 201973d..650afda 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-5-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c
index 3e7a7ed..7d69afc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u16.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c
index ffb9e6f..a5e822c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u32.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint16_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c
index 82396f5..7ab7399 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u64.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint32_t
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c
index 90a12c9..0fb8103 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_u_trunc-run-6-u8.c
@@ -1,7 +1,7 @@
 /* { dg-do run { target { riscv_v } } } */
 /* { dg-additional-options "-std=c99" } */
 
-#include "../vec_sat_arith.h"
+#include "vec_sat_arith.h"
 #include "vec_sat_data.h"
 
 #define T1 uint8_t