diff options
| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2024-07-11 15:38:45 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2024-07-11 15:38:45 +0100 |
| commit | 7c11fdd2cc11a7058e9643b6abf27831970ad2c9 (patch) | |
| tree | ea4e1e696b06b017611d7b8d3efac36f0fad67d1 /gcc/fortran/trans-array.h | |
| parent | 44fc801e97a8dc626a4806ff4124439003420b20 (diff) | |
| download | gcc-7c11fdd2cc11a7058e9643b6abf27831970ad2c9.zip gcc-7c11fdd2cc11a7058e9643b6abf27831970ad2c9.tar.gz gcc-7c11fdd2cc11a7058e9643b6abf27831970ad2c9.tar.bz2 | |
mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]
This patch fixes the backend pattern that was printing the wrong input
scalar register pair when inserting into lane 1.
Added a new test to force float-abi=hard so we can use scan-assembler to check
correct codegen.
gcc/ChangeLog:
PR target/115611
* config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of input
scalar register pair when lane = 1.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.
Diffstat (limited to 'gcc/fortran/trans-array.h')
0 files changed, 0 insertions, 0 deletions