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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2024-07-11 15:38:45 +0100 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2024-07-11 15:38:45 +0100 |
| commit | 7c11fdd2cc11a7058e9643b6abf27831970ad2c9 (patch) | |
| tree | ea4e1e696b06b017611d7b8d3efac36f0fad67d1 /gcc | |
| parent | 44fc801e97a8dc626a4806ff4124439003420b20 (diff) | |
| download | gcc-7c11fdd2cc11a7058e9643b6abf27831970ad2c9.zip gcc-7c11fdd2cc11a7058e9643b6abf27831970ad2c9.tar.gz gcc-7c11fdd2cc11a7058e9643b6abf27831970ad2c9.tar.bz2 | |
mve: Fix vsetq_lane for 64-bit elements with lane 1 [PR 115611]
This patch fixes the backend pattern that was printing the wrong input
scalar register pair when inserting into lane 1.
Added a new test to force float-abi=hard so we can use scan-assembler to check
correct codegen.
gcc/ChangeLog:
PR target/115611
* config/arm/mve.md (mve_vec_setv2di_internal): Fix printing of input
scalar register pair when lane = 1.
gcc/testsuite/ChangeLog:
* gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c: New test.
Diffstat (limited to 'gcc')
| -rw-r--r-- | gcc/config/arm/mve.md | 2 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c | 63 |
2 files changed, 64 insertions, 1 deletions
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 4b4d629..706a45c 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -6505,7 +6505,7 @@ if (elt == 0) return "vmov\t%e0, %Q1, %R1"; else - return "vmov\t%f0, %J1, %K1"; + return "vmov\t%f0, %Q1, %R1"; } [(set_attr "type" "mve_move")]) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c new file mode 100644 index 0000000..5aa3bc9 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_su64.c @@ -0,0 +1,63 @@ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-require-effective-target arm_hard_ok } */ +/* { dg-additional-options "-mfloat-abi=hard -O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "arm_mve.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* +**fn1: +** vmov d0, r0, r1 +** bx lr +*/ +uint64x2_t +fn1 (uint64_t a, uint64x2_t b) +{ + return vsetq_lane_u64 (a, b, 0); +} + +/* +**fn2: +** vmov d1, r0, r1 +** bx lr +*/ +uint64x2_t +fn2 (uint64_t a, uint64x2_t b) +{ + return vsetq_lane_u64 (a, b, 1); +} + +/* +**fn3: +** vmov d0, r0, r1 +** bx lr +*/ +int64x2_t +fn3 (int64_t a, int64x2_t b) +{ + return vsetq_lane_s64 (a, b, 0); +} + +/* +**fn4: +** vmov d1, r0, r1 +** bx lr +*/ +int64x2_t +fn4 (int64_t a, int64x2_t b) +{ + return vsetq_lane_s64 (a, b, 1); +} + + +#ifdef __cplusplus +} +#endif + +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ + |