Revert:

 	2007-09-06  Jan Hubicka  <jh@suse.cz>
 
	* i386.c (ix86_expand_lround, ix86_expand_round): Update call of
	real_2expN.

	2007-09-06  Richard Sandiford  <richard@codesourcery.com>

	* config/mips/mips.md (fixuns_truncdfsi2, fixuns_truncdfdi2)
	(fixuns_truncsfsi2, fixuns_truncsfdi2): Update calls to real_2expN.

	2007-09-05  Janis Johnson  <janis187@us.ibm.com>

	* optabs.c (expand_float): Convert unsigned integer as signed only
	if it provides sufficient accuracy; add mode argument to real_2expN.
	(expand_fix): Fix comment typos; extend binary float into mode
	wider than destination for converion to unsigned integer; add mode
	argument to real_2expN.
	* real.c (real_2expN): Add mode argument to special-case decimal
	float values.
	* real.h (real_2expN): Ditto.
	* fixed-value.c (check_real_for_fixed_mode): Add mode argument to
	real_2expN.
	(fixed_from_string): Ditto.
	(fixed_to_decimal): Ditto.
	(fixed_convert_from_real): Ditto.
	(real_convert_from_fixed): Ditto.
	* config/rs6000/rs6000.md (FP): Include DD and TD modes.
	* config/rs6000/dfp.md (extendddtd2, adddd3, addtd3, subdd3, subtd3,
	muldd3, multd3, divdd3, divtd3, cmpdd_internal1, cmptd_internal1,
	floatditd2, ftruncdd2, fixdddi2, ftrunctd2, fixddi2): New.

From-SVN: r128193

4 files changed, 7 insertions, 157 deletions

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index f6f80a0..dba72df 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -23144,7 +23144,7 @@ ix86_expand_lround (rtx op0, rtx op1)
 
   /* load nextafter (0.5, 0.0) */
   fmt = REAL_MODE_FORMAT (mode);
-  real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
+  real_2expN (&half_minus_pred_half, -(fmt->p) - 1);
   REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
 
   /* adj = copysign (0.5, op1) */
@@ -23555,7 +23555,7 @@ ix86_expand_round (rtx operand0, rtx operand1)
 
   /* load nextafter (0.5, 0.0) */
   fmt = REAL_MODE_FORMAT (mode);
-  real_2expN (&half_minus_pred_half, -(fmt->p) - 1, mode);
+  real_2expN (&half_minus_pred_half, -(fmt->p) - 1);
   REAL_ARITHMETIC (pred_half, MINUS_EXPR, dconsthalf, half_minus_pred_half);
 
   /* xa = xa + 0.5 */
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index f8333ec..6cda709 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -2805,7 +2805,7 @@
   rtx label2 = gen_label_rtx ();
   REAL_VALUE_TYPE offset;
 
-  real_2expN (&offset, 31, DFmode);
+  real_2expN (&offset, 31);
 
   if (reg1)			/* Turn off complaints about unreached code.  */
     {
@@ -2850,7 +2850,7 @@
   rtx label2 = gen_label_rtx ();
   REAL_VALUE_TYPE offset;
 
-  real_2expN (&offset, 63, DFmode);
+  real_2expN (&offset, 63);
 
   mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
   do_pending_stack_adjust ();
@@ -2892,7 +2892,7 @@
   rtx label2 = gen_label_rtx ();
   REAL_VALUE_TYPE offset;
 
-  real_2expN (&offset, 31, SFmode);
+  real_2expN (&offset, 31);
 
   mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
   do_pending_stack_adjust ();
@@ -2934,7 +2934,7 @@
   rtx label2 = gen_label_rtx ();
   REAL_VALUE_TYPE offset;
 
-  real_2expN (&offset, 63, SFmode);
+  real_2expN (&offset, 63);
 
   mips_emit_move (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
   do_pending_stack_adjust ();
diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index fa20f7d..0bc405a 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -405,151 +405,3 @@
 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
   [(set_attr "length" "8,8,8,20,20,16")])
 
-;; Hardware support for decimal floating point operations.
-
-(define_insn "extendddtd2"
-  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
-	(float_extend:TD (match_operand:DD 1 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "dctqpq %0,%1"
-  [(set_attr "type" "fp")])
-
-;; The result of drdpq is an even/odd register pair with the converted
-;; value in the even register and zero in the odd register.
-;; FIXME: Avoid the register move by using a reload constraint to ensure
-;; that the result is the first of the pair receiving the result of drdpq.
-
-(define_insn "trunctddd2"
-  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
-	(float_truncate:DD (match_operand:TD 1 "gpc_reg_operand" "f")))
-   (clobber (match_scratch:TD 2 "=f"))]
-  "TARGET_DFP"
-  "drdpq %2,%1\;fmr %0,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn "adddd3"
-  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
-	(plus:DD (match_operand:DD 1 "gpc_reg_operand" "%f")
-		 (match_operand:DD 2 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "dadd %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn "addtd3"
-  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
-	(plus:TD (match_operand:TD 1 "gpc_reg_operand" "%f")
-		 (match_operand:TD 2 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "daddq %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn "subdd3"
-  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
-	(minus:DD (match_operand:DD 1 "gpc_reg_operand" "f")
-		  (match_operand:DD 2 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "dsub %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn "subtd3"
-  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
-	(minus:TD (match_operand:TD 1 "gpc_reg_operand" "f")
-		  (match_operand:TD 2 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "dsubq %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn "muldd3"
-  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
-	(mult:DD (match_operand:DD 1 "gpc_reg_operand" "%f")
-		 (match_operand:DD 2 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "dmul %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn "multd3"
-  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
-	(mult:TD (match_operand:TD 1 "gpc_reg_operand" "%f")
-		 (match_operand:TD 2 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "dmulq %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn "divdd3"
-  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
-	(div:DD (match_operand:DD 1 "gpc_reg_operand" "f")
-		(match_operand:DD 2 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "ddiv %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn "divtd3"
-  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
-	(div:TD (match_operand:TD 1 "gpc_reg_operand" "f")
-		(match_operand:TD 2 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "ddivq %0,%1,%2"
-  [(set_attr "type" "fp")])
-
-(define_insn "*cmpdd_internal1"
-  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-	(compare:CCFP (match_operand:DD 1 "gpc_reg_operand" "f")
-		      (match_operand:DD 2 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "dcmpu %0,%1,%2"
-  [(set_attr "type" "fpcompare")])
-
-(define_insn "*cmptd_internal1"
-  [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-	(compare:CCFP (match_operand:TD 1 "gpc_reg_operand" "f")
-		      (match_operand:TD 2 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "dcmpuq %0,%1,%2"
-  [(set_attr "type" "fpcompare")])
-
-(define_insn "floatditd2"
-  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
-	(float:TD (match_operand:DI 1 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "dcffixq %0,%1"
-  [(set_attr "type" "fp")])
-
-;; Convert a decimal64 to a decimal64 whose value is an integer.
-;; This is the first stage of converting it to an integer type.
-
-(define_insn "ftruncdd2"
-  [(set (match_operand:DD 0 "gpc_reg_operand" "=f")
-	(fix:DD (match_operand:DD 1 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "drintn. 0,%0,%1,1"
-  [(set_attr "type" "fp")])
-
-;; Convert a decimal64 whose value is an integer to an actual integer.
-;; This is the second stage of converting decimal float to integer type.
-
-(define_insn "fixdddi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
-	(fix:DI (match_operand:DD 1 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "dctfix %0,%1"
-  [(set_attr "type" "fp")])
-
-;; Convert a decimal128 to a decimal128 whose value is an integer.
-;; This is the first stage of converting it to an integer type.
-
-(define_insn "ftrunctd2"
-  [(set (match_operand:TD 0 "gpc_reg_operand" "=f")
-	(fix:TD (match_operand:TD 1 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "drintnq. 0,%0,%1,1"
-  [(set_attr "type" "fp")])
-
-;; Convert a decimal128 whose value is an integer to an actual integer.
-;; This is the second stage of converting decimal float to integer type.
-
-(define_insn "fixtddi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
-	(fix:DI (match_operand:TD 1 "gpc_reg_operand" "f")))]
-  "TARGET_DFP"
-  "dctfixq %0,%1"
-  [(set_attr "type" "fp")])
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index debacdc..e3505d1 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -204,9 +204,7 @@
   (TF "!TARGET_IEEEQUAD
    && TARGET_HARD_FLOAT
    && (TARGET_FPRS || TARGET_E500_DOUBLE)
-   && TARGET_LONG_DOUBLE_128")
-  (DD "TARGET_DFP")
-  (TD "TARGET_DFP")])
+   && TARGET_LONG_DOUBLE_128")])
 
 ; Various instructions that come in SI and DI forms.
 ; A generic w/d attribute, for things like cmpw/cmpd.