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| author | Pan Li <pan2.li@intel.com> | 2024-12-04 13:53:52 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2024-12-04 16:47:38 +0800 |
| commit | fb64a7b0e1d7488e6e3ae96af8d97fd2226b6d21 (patch) | |
| tree | 6b34ff6548f542d80fbfac45675c77295cd9439e /gcc/config | |
| parent | b7c69cc072ef0da36439ebc55c513b48e68391b7 (diff) | |
| download | gcc-fb64a7b0e1d7488e6e3ae96af8d97fd2226b6d21.zip gcc-fb64a7b0e1d7488e6e3ae96af8d97fd2226b6d21.tar.gz gcc-fb64a7b0e1d7488e6e3ae96af8d97fd2226b6d21.tar.bz2 | |
RISC-V: Add assert for insn operand out of range access [PR117878][NFC]
According to the the initial analysis of PR117878, the ice comes from
the out-of-range operand access for recog_data.operand[]. Thus, add
one assert here to expose this explicitly.
PR target/117878
gcc/ChangeLog:
* config/riscv/riscv-v.cc (vlmax_avl_type_p): Add assert for
out of range access.
(nonvlmax_avl_type_p): Ditto.
Signed-off-by: Pan Li <pan2.li@intel.com>
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/riscv/riscv-v.cc | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index ee7a012..47bc0255 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -5174,6 +5174,9 @@ vlmax_avl_type_p (rtx_insn *rinsn) int index = get_attr_avl_type_idx (rinsn); if (index == INVALID_ATTRIBUTE) return false; + + gcc_assert (index < recog_data.n_operands); + rtx avl_type = recog_data.operand[index]; return INTVAL (avl_type) == VLMAX; } @@ -5222,6 +5225,9 @@ nonvlmax_avl_type_p (rtx_insn *rinsn) int index = get_attr_avl_type_idx (rinsn); if (index == INVALID_ATTRIBUTE) return false; + + gcc_assert (index < recog_data.n_operands); + rtx avl_type = recog_data.operand[index]; return INTVAL (avl_type) == NONVLMAX; } |