diff options
| author | Richard Kenner <kenner@gcc.gnu.org> | 1995-08-25 19:10:36 -0400 |
|---|---|---|
| committer | Richard Kenner <kenner@gcc.gnu.org> | 1995-08-25 19:10:36 -0400 |
| commit | f9f7f4c9f849c7c767265eb20d152d7fb27232a8 (patch) | |
| tree | a26da90c0b8406d5f255d18ea20927bcc29f9008 /gcc/config | |
| parent | fb409a19b2c9244fb32d6c215ec782fcbe6600d9 (diff) | |
| download | gcc-f9f7f4c9f849c7c767265eb20d152d7fb27232a8.zip gcc-f9f7f4c9f849c7c767265eb20d152d7fb27232a8.tar.gz gcc-f9f7f4c9f849c7c767265eb20d152d7fb27232a8.tar.bz2 | |
Added peephole definitions for Load/Store Base insns and eliminating redundant...
Added peephole definitions for Load/Store Base insns and eliminating
redundant load in an equivalent store/load sequence.
From-SVN: r10278
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/1750a/1750a.md | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/gcc/config/1750a/1750a.md b/gcc/config/1750a/1750a.md index b50b35b..2032e23 100644 --- a/gcc/config/1750a/1750a.md +++ b/gcc/config/1750a/1750a.md @@ -1275,5 +1275,59 @@ "INTVAL(operands[2]) == -1" "soj r%0,%3") +;; Load Base +(define_peephole + [(set (match_operand:QI 0 "register_operand" "=r") + (mem:QI (plus:QI (match_operand:QI 1 "register_operand" "x") + (match_operand:QI 2 "immediate_operand" "L")))) + ] + "REGNO(operands[0]) == 2 && REGNO(operands[1]) >= 12 + && INTVAL(operands[2]) <= 255" + "lb r%1,%2") + +;; Double Load Base +(define_peephole + [(set (match_operand:HI 0 "register_operand" "=r") + (mem:HI (plus:QI (match_operand:QI 1 "register_operand" "x") + (match_operand:QI 2 "immediate_operand" "L")))) + ] + "REGNO(operands[0]) == 0 && REGNO(operands[1]) >= 12 + && INTVAL(operands[2]) <= 255" + "dlb r%1,%2") + +;; Store Base +(define_peephole + [(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "x") + (match_operand:QI 1 "immediate_operand" "L"))) + (match_operand:QI 2 "register_operand" "r")) + ] + "REGNO(operands[2]) == 2 && REGNO(operands[0]) >= 12 + && INTVAL(operands[1]) <= 255" + "stb r%0,%1") + +;; Double Store Base +(define_peephole + [(set (mem:HI (plus:QI (match_operand:QI 0 "register_operand" "x") + (match_operand:QI 1 "immediate_operand" "L"))) + (match_operand:HI 2 "register_operand" "r")) + ] + "REGNO(operands[2]) == 0 && REGNO(operands[0]) >= 12 + && INTVAL(operands[1]) <= 255" + "stb r%0,%1") + +;; Eliminate the redundant load in a store/load sequence +(define_peephole + [(set (mem:QI (plus:QI (match_operand:QI 0 "register_operand" "r") + (match_operand:QI 1 "immediate_operand" "i"))) + (match_operand:QI 2 "register_operand" "r")) + (set (match_operand:QI 3 "register_operand" "=r") + (mem:QI (plus:QI (match_operand:QI 4 "register_operand" "r") + (match_operand:QI 5 "immediate_operand" "i")))) + ] + "REGNO(operands[2]) == REGNO(operands[3]) && + REGNO(operands[0]) == REGNO(operands[4]) && + INTVAL(operands[1]) == INTVAL(operands[5])" + "st r%2,%1,r%0 ; eliminated previous redundant load") + ;;;End. |