sparc.opt (mlra): New target option.

	* config/sparc/sparc.opt (mlra): New target option.
	* config/sparc/sparc.c (TARGET_LRA_P): Define to...
	(sparc_lra_p): ...this.  New function.
	(D_MODES, DF_MODES): Add missing cast.
	* config/sparc/sparc.md (*movsi_lo_sum, *movsi_high): Do not
	provide these insns when flag_pic.
	(sethi_di_medlow, losum_di_medlow, seth44, setm44, setl44, sethh,
	setlm, sethm, setlo, embmedany_sethi, embmedany_losum,
	embmedany_brsum, embmedany_textuhi, embmedany_texthi,
	embmedany_textulo, embmedany_textlo): Likewise.
	(sethi_di_medlow_embmedany_pic): Provide it only when flag_pic.

Co-Authored-By: David S. Miller <davem@davemloft.net>

From-SVN: r243135

3 files changed, 37 insertions, 28 deletions

diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index a70a0ad..e17552a 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -639,6 +639,7 @@ static const char *sparc_mangle_type (const_tree);
 static void sparc_trampoline_init (rtx, tree, rtx);
 static machine_mode sparc_preferred_simd_mode (machine_mode);
 static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass);
+static bool sparc_lra_p (void);
 static bool sparc_print_operand_punct_valid_p (unsigned char);
 static void sparc_print_operand (FILE *, rtx, int);
 static void sparc_print_operand_address (FILE *, machine_mode, rtx);
@@ -836,7 +837,7 @@ char sparc_hard_reg_printed[8];
 #endif
 
 #undef TARGET_LRA_P
-#define TARGET_LRA_P hook_bool_void_false
+#define TARGET_LRA_P sparc_lra_p
 
 #undef TARGET_LEGITIMATE_ADDRESS_P
 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p
@@ -4787,7 +4788,7 @@ enum sparc_mode_class {
   ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE))
 
 /* Modes for double-word and smaller quantities.  */
-#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
+#define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
 
 /* Modes for quad-word and smaller quantities.  */
 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
@@ -4799,7 +4800,7 @@ enum sparc_mode_class {
 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
 
 /* Modes for double-float and smaller quantities.  */
-#define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
+#define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE))
 
 /* Modes for quad-float and smaller quantities.  */
 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE))
@@ -12248,6 +12249,14 @@ sparc_preferred_reload_class (rtx x, reg_class_t rclass)
   return rclass;
 }
 
+/* Return true if we use LRA instead of reload pass.  */
+
+static bool
+sparc_lra_p (void)
+{
+  return TARGET_LRA;
+}
+
 /* Output a wide multiply instruction in V8+ mode.  INSN is the instruction,
    OPERANDS are its operands and OPCODE is the mnemonic to be used.  */
 
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index f33c391..896ce4b 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -1568,13 +1568,13 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
                    (match_operand:SI 2 "immediate_operand" "in")))]
-  ""
+  "!flag_pic"
   "or\t%1, %%lo(%a2), %0")
 
 (define_insn "*movsi_high"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(high:SI (match_operand:SI 1 "immediate_operand" "in")))]
-  ""
+  "!flag_pic"
   "sethi\t%%hi(%a1), %0")
 
 ;; The next two patterns must wrap the SYMBOL_REF in an UNSPEC
@@ -1846,27 +1846,27 @@
 (define_insn "*sethi_di_medlow_embmedany_pic"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (match_operand:DI 1 "medium_pic_operand" "")))]
-  "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && check_pic (1)"
+  "(TARGET_CM_MEDLOW || TARGET_CM_EMBMEDANY) && flag_pic && check_pic (1)"
   "sethi\t%%hi(%a1), %0")
 
 (define_insn "*sethi_di_medlow"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (match_operand:DI 1 "symbolic_operand" "")))]
-  "TARGET_CM_MEDLOW && check_pic (1)"
+  "TARGET_CM_MEDLOW && !flag_pic"
   "sethi\t%%hi(%a1), %0")
 
 (define_insn "*losum_di_medlow"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "symbolic_operand" "")))]
-  "TARGET_CM_MEDLOW"
+  "TARGET_CM_MEDLOW && !flag_pic"
   "or\t%1, %%lo(%a2), %0")
 
 (define_insn "seth44"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
 			    UNSPEC_SETH44)))]
-  "TARGET_CM_MEDMID"
+  "TARGET_CM_MEDMID && !flag_pic"
   "sethi\t%%h44(%a1), %0")
 
 (define_insn "setm44"
@@ -1874,28 +1874,28 @@
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
 			      UNSPEC_SETM44)))]
-  "TARGET_CM_MEDMID"
+  "TARGET_CM_MEDMID && !flag_pic"
   "or\t%1, %%m44(%a2), %0")
 
 (define_insn "setl44"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "symbolic_operand" "")))]
-  "TARGET_CM_MEDMID"
+  "TARGET_CM_MEDMID && !flag_pic"
   "or\t%1, %%l44(%a2), %0")
 
 (define_insn "sethh"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
 			    UNSPEC_SETHH)))]
-  "TARGET_CM_MEDANY"
+  "TARGET_CM_MEDANY && !flag_pic"
   "sethi\t%%hh(%a1), %0")
 
 (define_insn "setlm"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
 			    UNSPEC_SETLM)))]
-  "TARGET_CM_MEDANY"
+  "TARGET_CM_MEDANY && !flag_pic"
   "sethi\t%%lm(%a1), %0")
 
 (define_insn "sethm"
@@ -1903,49 +1903,49 @@
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
 			      UNSPEC_EMB_SETHM)))]
-  "TARGET_CM_MEDANY"
+  "TARGET_CM_MEDANY && !flag_pic"
   "or\t%1, %%hm(%a2), %0")
 
 (define_insn "setlo"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "symbolic_operand" "")))]
-  "TARGET_CM_MEDANY"
+  "TARGET_CM_MEDANY && !flag_pic"
   "or\t%1, %%lo(%a2), %0")
 
 (define_insn "embmedany_sethi"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "data_segment_operand" "")]
 			    UNSPEC_EMB_HISUM)))]
-  "TARGET_CM_EMBMEDANY && check_pic (1)"
+  "TARGET_CM_EMBMEDANY && !flag_pic"
   "sethi\t%%hi(%a1), %0")
 
 (define_insn "embmedany_losum"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "data_segment_operand" "")))]
-  "TARGET_CM_EMBMEDANY"
+  "TARGET_CM_EMBMEDANY && !flag_pic"
   "add\t%1, %%lo(%a2), %0")
 
 (define_insn "embmedany_brsum"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
 	           UNSPEC_EMB_HISUM))]
-  "TARGET_CM_EMBMEDANY"
+  "TARGET_CM_EMBMEDANY && !flag_pic"
   "add\t%1, %_, %0")
 
 (define_insn "embmedany_textuhi"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")]
 			    UNSPEC_EMB_TEXTUHI)))]
-  "TARGET_CM_EMBMEDANY && check_pic (1)"
+  "TARGET_CM_EMBMEDANY && !flag_pic"
   "sethi\t%%uhi(%a1), %0")
 
 (define_insn "embmedany_texthi"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (high:DI (unspec:DI [(match_operand:DI 1 "text_segment_operand" "")]
 			    UNSPEC_EMB_TEXTHI)))]
-  "TARGET_CM_EMBMEDANY && check_pic (1)"
+  "TARGET_CM_EMBMEDANY && !flag_pic"
   "sethi\t%%hi(%a1), %0")
 
 (define_insn "embmedany_textulo"
@@ -1953,14 +1953,14 @@
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (unspec:DI [(match_operand:DI 2 "text_segment_operand" "")]
 			      UNSPEC_EMB_TEXTULO)))]
-  "TARGET_CM_EMBMEDANY"
+  "TARGET_CM_EMBMEDANY && !flag_pic"
   "or\t%1, %%ulo(%a2), %0")
 
 (define_insn "embmedany_textlo"
   [(set (match_operand:DI 0 "register_operand" "=r")
         (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
                    (match_operand:DI 2 "text_segment_operand" "")))]
-  "TARGET_CM_EMBMEDANY"
+  "TARGET_CM_EMBMEDANY && !flag_pic"
   "or\t%1, %%lo(%a2), %0")
 
 ;; Now some patterns to help reload out a bit.
@@ -1968,9 +1968,7 @@
   [(parallel [(match_operand:DI 0 "register_operand" "=r")
               (match_operand:DI 1 "immediate_operand" "")
               (match_operand:TI 2 "register_operand" "=&r")])]
-  "(TARGET_CM_MEDANY
-    || TARGET_CM_EMBMEDANY)
-   && !flag_pic"
+  "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) && !flag_pic"
 {
   sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
   DONE;
@@ -1980,9 +1978,7 @@
   [(parallel [(match_operand:DI 0 "register_operand" "=r")
               (match_operand:DI 1 "immediate_operand" "")
               (match_operand:TI 2 "register_operand" "=&r")])]
-  "(TARGET_CM_MEDANY
-    || TARGET_CM_EMBMEDANY)
-   && !flag_pic"
+  "(TARGET_CM_MEDANY || TARGET_CM_EMBMEDANY) && !flag_pic"
 {
   sparc_emit_set_symbolic_const64 (operands[0], operands[1], operands[2]);
   DONE;
diff --git a/gcc/config/sparc/sparc.opt b/gcc/config/sparc/sparc.opt
index 1be7800..973fe6f 100644
--- a/gcc/config/sparc/sparc.opt
+++ b/gcc/config/sparc/sparc.opt
@@ -57,6 +57,10 @@ msoft-quad-float
 Target Report RejectNegative InverseMask(HARD_QUAD)
 Do not use hardware quad fp instructions.
 
+mlra
+Target Report Mask(LRA)
+Enable Local Register Allocation.
+
 mv8plus
 Target Report Mask(V8PLUS)
 Compile for V8+ ABI.