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| author | Maxim Kuvyrkov <mkuvyrkov@ispras.ru> | 2007-02-02 16:57:18 +0000 |
|---|---|---|
| committer | Maxim Kuvyrkov <mkuvyrkov@gcc.gnu.org> | 2007-02-02 16:57:18 +0000 |
| commit | f6ec1d11632ab0a33dacb5043ac4819d5a91759e (patch) | |
| tree | a4617b210981196e4316dfc4c93c9716e964254d /gcc/config | |
| parent | b4e18eee4b56ed8d4003d1fb92acb5f7dbf43748 (diff) | |
| download | gcc-f6ec1d11632ab0a33dacb5043ac4819d5a91759e.zip gcc-f6ec1d11632ab0a33dacb5043ac4819d5a91759e.tar.gz gcc-f6ec1d11632ab0a33dacb5043ac4819d5a91759e.tar.bz2 | |
re PR target/29682 (ICE: in change_pattern, at haifa-sched.c:4066 with -O3 -msched-control-spec)
PR target/29682
* config/ia64/ia64.c (ia64_speculate_insn): Restrict to memory loads to
general or fp registers. Add comments.
* config/ia64/ia64.md (reg_pred_prefix): Add comment.
PR target/29682
* gcc-target/ia64/pr29682.c: New test.
From-SVN: r121510
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/ia64/ia64.c | 16 | ||||
| -rw-r--r-- | gcc/config/ia64/ia64.md | 3 |
2 files changed, 17 insertions, 2 deletions
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c index ca154f8..aebfc1a 100644 --- a/gcc/config/ia64/ia64.c +++ b/gcc/config/ia64/ia64.c @@ -6786,13 +6786,19 @@ ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat) if (GET_CODE (pat) == COND_EXEC) pat = COND_EXEC_CODE (pat); + /* This should be a SET ... */ if (GET_CODE (pat) != SET) return -1; + reg = SET_DEST (pat); - if (!REG_P (reg)) + /* ... to the general/fp register ... */ + if (!REG_P (reg) || !(GR_REGNO_P (REGNO (reg)) || FP_REGNO_P (REGNO (reg)))) return -1; - mem = SET_SRC (pat); + /* ... from the mem ... */ + mem = SET_SRC (pat); + + /* ... that can, possibly, be a zero_extend ... */ if (GET_CODE (mem) == ZERO_EXTEND) { mem = XEXP (mem, 0); @@ -6801,6 +6807,7 @@ ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat) else extend_p = false; + /* ... or a speculative load. */ if (GET_CODE (mem) == UNSPEC) { int code; @@ -6817,8 +6824,12 @@ ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat) mem = XVECEXP (mem, 0, 0); gcc_assert (MEM_P (mem)); } + + /* Source should be a mem ... */ if (!MEM_P (mem)) return -1; + + /* ... addressed by a register. */ mem_reg = XEXP (mem, 0); if (!REG_P (mem_reg)) return -1; @@ -6835,6 +6846,7 @@ ia64_speculate_insn (rtx insn, ds_t ts, rtx *new_pat) extract_insn_cached (insn); gcc_assert (reg == recog_data.operand[0] && mem == recog_data.operand[1]); + *new_pat = ia64_gen_spec_insn (insn, ts, mode_no, gen_p != 0, extend_p); return gen_p; diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index f25ad76..e573c55 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -474,6 +474,9 @@ (define_mode_attr mem_constr [(BI "*m") (QI "m") (HI "m") (SI "m") (DI "m,Q") (SF "Q,m") (DF "Q,m") (XF "m") (TI "Q")]) +;; Define register predicate prefix. +;; We can generate speculative loads only for general and fp registers - this +;; is constrainted in ia64.c: ia64_speculate_insn (). (define_mode_attr reg_pred_prefix [(BI "gr") (QI "gr") (HI "gr") (SI "gr") (DI "grfr") (SF "grfr") (DF "grfr") (XF "fr") (TI "fr")]) (define_mode_attr ld_class [(BI "ld") (QI "ld") (HI "ld") (SI "ld") (DI "ld,fld") (SF "fld,ld") (DF "fld,ld") (XF "fld") (TI "fldp")]) |