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| author | Haochen Gui <guihaoc@gcc.gnu.org> | 2021-11-17 16:16:02 +0800 |
|---|---|---|
| committer | Haochen Gui <guihaoc@gcc.gnu.org> | 2021-11-23 16:31:59 +0800 |
| commit | f4eae6450e46224454ce067ac43bd7e9f66fc18b (patch) | |
| tree | 5c4790b7651c13829bc2a245740e95589162cfad /gcc/config | |
| parent | 1ddf11d3647f68e0c31016935f19d843d54030b4 (diff) | |
| download | gcc-f4eae6450e46224454ce067ac43bd7e9f66fc18b.zip gcc-f4eae6450e46224454ce067ac43bd7e9f66fc18b.tar.gz gcc-f4eae6450e46224454ce067ac43bd7e9f66fc18b.tar.bz2 | |
rs6000: Optimize code generation of vec_reve [PR100868]
gcc/
PR target/100868
* config/rs6000/altivec.md (altivec_vreve<mode>2 for VEC_K): Use
xxbrq for v16qi, xxbrq + xxbrh for v8hi and xxbrq + xxbrw for v4si
or v4sf when p9_vector is set.
(altivec_vreve<mode>2 for VEC_64): Defined. Implemented by xxswapd.
gcc/testsuite/
PR target/100868
* gcc.target/powerpc/vec_reve_1.c: New test.
* gcc.target/powerpc/vec_reve_2.c: Likewise.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 46 |
1 files changed, 44 insertions, 2 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index a057218..ef43211 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -3984,12 +3984,43 @@ DONE; }) +;; Vector reverse elements for V16QI V8HI V4SI V4SF (define_expand "altivec_vreve<mode>2" - [(set (match_operand:VEC_A 0 "register_operand" "=v") - (unspec:VEC_A [(match_operand:VEC_A 1 "register_operand" "v")] + [(set (match_operand:VEC_K 0 "register_operand" "=v") + (unspec:VEC_K [(match_operand:VEC_K 1 "register_operand" "v")] UNSPEC_VREVEV))] "TARGET_ALTIVEC" { + if (TARGET_P9_VECTOR) + { + if (<MODE>mode == V16QImode) + emit_insn (gen_p9_xxbrq_v16qi (operands[0], operands[1])); + else if (<MODE>mode == V8HImode) + { + rtx subreg1 = simplify_gen_subreg (V1TImode, operands[1], + <MODE>mode, 0); + rtx temp = gen_reg_rtx (V1TImode); + emit_insn (gen_p9_xxbrq_v1ti (temp, subreg1)); + rtx subreg2 = simplify_gen_subreg (<MODE>mode, temp, + V1TImode, 0); + emit_insn (gen_p9_xxbrh_v8hi (operands[0], subreg2)); + } + else /* V4SI and V4SF. */ + { + rtx subreg1 = simplify_gen_subreg (V1TImode, operands[1], + <MODE>mode, 0); + rtx temp = gen_reg_rtx (V1TImode); + emit_insn (gen_p9_xxbrq_v1ti (temp, subreg1)); + rtx subreg2 = simplify_gen_subreg (<MODE>mode, temp, + V1TImode, 0); + if (<MODE>mode == V4SImode) + emit_insn (gen_p9_xxbrw_v4si (operands[0], subreg2)); + else + emit_insn (gen_p9_xxbrw_v4sf (operands[0], subreg2)); + } + DONE; + } + int i, j, size, num_elements; rtvec v = rtvec_alloc (16); rtx mask = gen_reg_rtx (V16QImode); @@ -4008,6 +4039,17 @@ DONE; }) +;; Vector reverse elements for V2DI V2DF +(define_expand "altivec_vreve<mode>2" + [(set (match_operand:VEC_64 0 "register_operand" "=v") + (unspec:VEC_64 [(match_operand:VEC_64 1 "register_operand" "v")] + UNSPEC_VREVEV))] + "TARGET_ALTIVEC" +{ + emit_insn (gen_xxswapd_<mode> (operands[0], operands[1])); + DONE; +}) + ;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL, ;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell. (define_insn "altivec_lvlx" |