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authorAndrew Pinski <apinski@marvell.com>2022-08-19 17:46:40 +0000
committerAndrew Pinski <apinski@marvell.com>2022-08-24 11:30:44 -0700
commite5e6983c3da53729e58a32af1d531ea74b3dbf5d (patch)
tree1de40f51a76673e5c4953b1a48e4a9e6bda3bd00 /gcc/config
parentcb2daf5acce003300ee948a89860c0d13ebcae79 (diff)
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Fix PR 106601: __builtin_bswap16 code gen could be improved with ZBB enabled
The default expansion for bswap16 is two extractions (shift/and) followed by an insertation (ior) and then a zero extend. This can be improved with ZBB enabled to just full byteswap followed by a (logical) shift right. This patch adds a new pattern for this which does that. OK? Built and tested on riscv32-linux-gnu and riscv64-linux-gnu. gcc/ChangeLog: PR target/106601 * config/riscv/bitmanip.md (bswaphi2): New pattern. gcc/testsuite/ChangeLog: PR target/106601 * gcc.target/riscv/zbb_32_bswap-2.c: New test. * gcc.target/riscv/zbb_bswap-2.c: New test.
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/riscv/bitmanip.md24
1 files changed, 24 insertions, 0 deletions
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index c7ba667..c438328 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -276,6 +276,30 @@
"rev8\t%0,%1"
[(set_attr "type" "bitmanip")])
+;; HI bswap can be emulated using SI/DI bswap followed
+;; by a logical shift right
+;; SI bswap for TARGET_64BIT is already similarly in
+;; the common code.
+(define_expand "bswaphi2"
+ [(set (match_operand:HI 0 "register_operand" "=r")
+ (bswap:HI (match_operand:HI 1 "register_operand" "r")))]
+ "TARGET_ZBB"
+{
+ rtx tmp = gen_reg_rtx (word_mode);
+ rtx newop1 = gen_lowpart (word_mode, operands[1]);
+ if (TARGET_64BIT)
+ emit_insn (gen_bswapdi2 (tmp, newop1));
+ else
+ emit_insn (gen_bswapsi2 (tmp, newop1));
+ rtx tmp1 = gen_reg_rtx (word_mode);
+ if (TARGET_64BIT)
+ emit_insn (gen_lshrdi3 (tmp1, tmp, GEN_INT (64 - 16)));
+ else
+ emit_insn (gen_lshrsi3 (tmp1, tmp, GEN_INT (32 - 16)));
+ emit_move_insn (operands[0], gen_lowpart (HImode, tmp1));
+ DONE;
+})
+
(define_insn "<bitmanip_optab><mode>3"
[(set (match_operand:X 0 "register_operand" "=r")
(bitmanip_minmax:X (match_operand:X 1 "register_operand" "r")