vect: Add support for fmax and fmin reductions

This patch adds support for reductions involving calls to fmax*()
and fmin*(), without the -ffast-math flags that allow them to be
converted to MAX_EXPR and MIN_EXPR.

gcc/
	* doc/md.texi (reduc_fmin_scal_@var{m}): Document.
	(reduc_fmax_scal_@var{m}): Likewise.
	* optabs.def (reduc_fmax_scal_optab): New optab.
	(reduc_fmin_scal_optab): Likewise
	* internal-fn.def (REDUC_FMAX, REDUC_FMIN): New functions.
	* tree-vect-loop.c (reduction_fn_for_scalar_code): Handle
	CASE_CFN_FMAX and CASE_CFN_FMIN.
	(neutral_op_for_reduction): Likewise.
	(needs_fold_left_reduction_p): Likewise.
	* config/aarch64/iterators.md (FMAXMINV): New iterator.
	(fmaxmin): Handle UNSPEC_FMAXNMV and UNSPEC_FMINNMV.
	* config/aarch64/aarch64-simd.md (reduc_<optab>_scal_<mode>): Fix
	unspec mode.
	(reduc_<fmaxmin>_scal_<mode>): New pattern.
	* config/aarch64/aarch64-sve.md (reduc_<fmaxmin>_scal_<mode>):
	Likewise.

gcc/testsuite/
	* gcc.dg/vect/vect-fmax-1.c: New test.
	* gcc.dg/vect/vect-fmax-2.c: Likewise.
	* gcc.dg/vect/vect-fmax-3.c: Likewise.
	* gcc.dg/vect/vect-fmin-1.c: New test.
	* gcc.dg/vect/vect-fmin-2.c: Likewise.
	* gcc.dg/vect/vect-fmin-3.c: Likewise.
	* gcc.target/aarch64/fmaxnm_1.c: Likewise.
	* gcc.target/aarch64/fmaxnm_2.c: Likewise.
	* gcc.target/aarch64/fminnm_1.c: Likewise.
	* gcc.target/aarch64/fminnm_2.c: Likewise.
	* gcc.target/aarch64/sve/fmaxnm_2.c: Likewise.
	* gcc.target/aarch64/sve/fmaxnm_3.c: Likewise.
	* gcc.target/aarch64/sve/fminnm_2.c: Likewise.
	* gcc.target/aarch64/sve/fminnm_3.c: Likewise.

3 files changed, 28 insertions, 2 deletions

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 1020cd9..8e61dd9 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -3592,8 +3592,8 @@
 ;; gimple_fold'd to the IFN_REDUC_(MAX|MIN) function.  (This is FP smax/smin).
 (define_expand "reduc_<optab>_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
-   (unspec:VHSDF [(match_operand:VHSDF 1 "register_operand")]
-		  FMAXMINV)]
+   (unspec:<VEL> [(match_operand:VHSDF 1 "register_operand")]
+		 FMAXMINV)]
   "TARGET_SIMD"
   {
     rtx elt = aarch64_endian_lane_rtx (<MODE>mode, 0);
@@ -3605,6 +3605,17 @@
   }
 )
 
+(define_expand "reduc_<fmaxmin>_scal_<mode>"
+  [(match_operand:<VEL> 0 "register_operand")
+   (unspec:<VEL> [(match_operand:VHSDF 1 "register_operand")]
+		 FMAXMINNMV)]
+  "TARGET_SIMD"
+  {
+    emit_insn (gen_reduc_<optab>_scal_<mode> (operands[0], operands[1]));
+    DONE;
+  }
+)
+
 ;; Likewise for integer cases, signed and unsigned.
 (define_expand "reduc_<optab>_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index 0f5bf5e..9ef9688 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -8566,6 +8566,17 @@
   }
 )
 
+(define_expand "reduc_<fmaxmin>_scal_<mode>"
+  [(match_operand:<VEL> 0 "register_operand")
+   (unspec:<VEL> [(match_operand:SVE_FULL_F 1 "register_operand")]
+		 FMAXMINNMV)]
+  "TARGET_SVE"
+  {
+    emit_insn (gen_reduc_<optab>_scal_<mode> (operands[0], operands[1]));
+    DONE;
+  }
+)
+
 ;; Predicated floating-point tree reductions.
 (define_insn "@aarch64_pred_reduc_<optab>_<mode>"
   [(set (match_operand:<VEL> 0 "register_operand" "=w")
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 2c58d55..0b34e7f 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -2519,6 +2519,8 @@
 (define_int_iterator FMAXMINV [UNSPEC_FMAXV UNSPEC_FMINV
 			       UNSPEC_FMAXNMV UNSPEC_FMINNMV])
 
+(define_int_iterator FMAXMINNMV [UNSPEC_FMAXNMV UNSPEC_FMINNMV])
+
 (define_int_iterator SVE_INT_ADDV [UNSPEC_SADDV UNSPEC_UADDV])
 
 (define_int_iterator USADDLP [UNSPEC_SADDLP UNSPEC_UADDLP])
@@ -3225,8 +3227,10 @@
 
 (define_int_attr fmaxmin [(UNSPEC_FMAX "fmax_nan")
 			  (UNSPEC_FMAXNM "fmax")
+			  (UNSPEC_FMAXNMV "fmax")
 			  (UNSPEC_FMIN "fmin_nan")
 			  (UNSPEC_FMINNM "fmin")
+			  (UNSPEC_FMINNMV "fmin")
 			  (UNSPEC_COND_FMAXNM "fmax")
 			  (UNSPEC_COND_FMINNM "fmin")])