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| author | Alex Velenko <Alex.Velenko@arm.com> | 2014-01-23 14:48:40 +0000 |
|---|---|---|
| committer | Kyrylo Tkachov <ktkachov@gcc.gnu.org> | 2014-01-23 14:48:40 +0000 |
| commit | dafb9b6489ef1b45a0831e46d85aa9933de4428e (patch) | |
| tree | 3474cbb6a9a7a45a2328c8e4ac4d5d75dd9e6a94 /gcc/config | |
| parent | 89b4515c8c2a20b743febb65ce3df92ede698222 (diff) | |
| download | gcc-dafb9b6489ef1b45a0831e46d85aa9933de4428e.zip gcc-dafb9b6489ef1b45a0831e46d85aa9933de4428e.tar.gz gcc-dafb9b6489ef1b45a0831e46d85aa9933de4428e.tar.bz2 | |
[AArch64_BE 2/4] Big-Endian lane numbering fix
2013-01-23 Alex Velenko <Alex.Velenko@arm.com>
* config/aarch64/aarch64-simd.md
(aarch64_be_checked_get_lane<mode>): New define_expand.
* config/aarch64/aarch64-simd-builtins.def
(BUILTIN_VALL (GETLANE, be_checked_get_lane, 0):
New builtin definition.
* config/aarch64/arm_neon.h: (__aarch64_vget_lane_any):
Use new safe be builtin.
From-SVN: r206970
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd-builtins.def | 1 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64-simd.md | 14 | ||||
| -rw-r--r-- | gcc/config/aarch64/arm_neon.h | 2 |
3 files changed, 16 insertions, 1 deletions
diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def index 034afbf..185281a 100644 --- a/gcc/config/aarch64/aarch64-simd-builtins.def +++ b/gcc/config/aarch64/aarch64-simd-builtins.def @@ -49,6 +49,7 @@ BUILTIN_VALL (GETLANE, get_lane, 0) VAR1 (GETLANE, get_lane, 0, di) + BUILTIN_VALL (GETLANE, be_checked_get_lane, 0) BUILTIN_VD_RE (REINTERP, reinterpretdi, 0) BUILTIN_VDC (REINTERP, reinterpretv8qi, 0) diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 1454a7e..14eb7d0 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2062,6 +2062,20 @@ [(set_attr "type" "neon_to_gp<q>")] ) +(define_expand "aarch64_be_checked_get_lane<mode>" + [(match_operand:<VEL> 0 "aarch64_simd_nonimmediate_operand") + (match_operand:VALL 1 "register_operand") + (match_operand:SI 2 "immediate_operand")] + "TARGET_SIMD" + { + operands[2] = GEN_INT (ENDIAN_LANE_N (<MODE>mode, INTVAL (operands[2]))); + emit_insn (gen_aarch64_get_lane<mode> (operands[0], + operands[1], + operands[2])); + DONE; + } +) + ;; Lane extraction of a value, neither sign nor zero extension ;; is guaranteed so upper bits should be considered undefined. (define_insn "aarch64_get_lane<mode>" diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index ac87d70..1dcff67 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -457,7 +457,7 @@ typedef struct poly16x8x4_t #define __aarch64_vget_lane_any(__size, __cast_ret, __cast_a, __a, __b) \ (__cast_ret \ - __builtin_aarch64_get_lane##__size (__cast_a __a, __b)) + __builtin_aarch64_be_checked_get_lane##__size (__cast_a __a, __b)) #define __aarch64_vget_lane_f32(__a, __b) \ __aarch64_vget_lane_any (v2sf, , , __a, __b) |