arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.

2016-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.
    (TARGET_HAVE_LDACQD): New macro.
    * config/arm/sync.md (atomic_loaddi): Use TARGET_HAVE_LDACQD rather
    than TARGET_HAVE_LDACQ.
    (arm_load_acquire_exclusivedi): Likewise.
    (arm_store_release_exclusivedi): Likewise.

    libgcc/
    * gcc.target/arm/atomic-comp-swap-release-acquire.c: Rename into ...
    * gcc.target/arm/atomic-comp-swap-release-acquire-1.c: This.
    * gcc.target/arm/atomic-op-acq_rel.c: Rename into ...
    * gcc.target/arm/atomic-op-acq_rel-1.c: This.
    * gcc.target/arm/atomic-op-acquire.c: Rename into ...
    * gcc.target/arm/atomic-op-acquire-1.c: This.
    * gcc.target/arm/atomic-op-char.c: Rename into ...
    * gcc.target/arm/atomic-op-char-1.c: This.
    * gcc.target/arm/atomic-op-consume.c: Rename into ...
    * gcc.target/arm/atomic-op-consume-1.c: This.
    * gcc.target/arm/atomic-op-int.c: Rename into ...
    * gcc.target/arm/atomic-op-int-1.c: This.
    * gcc.target/arm/atomic-op-relaxed.c: Rename into ...
    * gcc.target/arm/atomic-op-relaxed-1.c: This.
    * gcc.target/arm/atomic-op-release.c: Rename into ...
    * gcc.target/arm/atomic-op-release-1.c: This.
    * gcc.target/arm/atomic-op-seq_cst.c: Rename into ...
    * gcc.target/arm/atomic-op-seq_cst-1.c: This.
    * gcc.target/arm/atomic-op-short.c: Rename into ...
    * gcc.target/arm/atomic-op-short-1.c: This.
    * gcc.target/arm/atomic-comp-swap-release-acquire-2.c: New test.
    * gcc.target/arm/atomic-op-acq_rel-2.c: Likewise.
    * gcc.target/arm/atomic-op-acquire-2.c: Likewise.
    * gcc.target/arm/atomic-op-char-2.c: Likewise.
    * gcc.target/arm/atomic-op-consume-2.c: Likewise.
    * gcc.target/arm/atomic-op-int-2.c: Likewise.
    * gcc.target/arm/atomic-op-relaxed-2.c: Likewise.
    * gcc.target/arm/atomic-op-release-2.c: Likewise.
    * gcc.target/arm/atomic-op-seq_cst-2.c: Likewise.
    * gcc.target/arm/atomic-op-short-2.c: Likewise.

From-SVN: r238348

2 files changed, 10 insertions, 5 deletions

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 317885c..c7149d1 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -261,7 +261,12 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
 			     || arm_arch7) && arm_arch_notm)
 
 /* Nonzero if this chip supports load-acquire and store-release.  */
-#define TARGET_HAVE_LDACQ	(TARGET_ARM_ARCH >= 8 && arm_arch_notm)
+#define TARGET_HAVE_LDACQ	(TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
+
+/* Nonzero if this chip supports LDAEXD and STLEXD.  */
+#define TARGET_HAVE_LDACQEXD	(TARGET_ARM_ARCH >= 8	\
+				 && TARGET_32BIT	\
+				 && arm_arch_notm)
 
 /* Nonzero if this chip provides the MOVW and MOVT instructions.  */
 #define TARGET_HAVE_MOVT	(arm_arch_thumb2 || arm_arch8)
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index abcfbcb..d10ede4 100644
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -117,7 +117,7 @@
   [(match_operand:DI 0 "s_register_operand")		;; val out
    (match_operand:DI 1 "mem_noofs_operand")		;; memory
    (match_operand:SI 2 "const_int_operand")]		;; model
-  "(TARGET_HAVE_LDREXD || TARGET_HAVE_LPAE || TARGET_HAVE_LDACQ)
+  "(TARGET_HAVE_LDREXD || TARGET_HAVE_LPAE || TARGET_HAVE_LDACQEXD)
    && ARM_DOUBLEWORD_ALIGN"
 {
   memmodel model = memmodel_from_int (INTVAL (operands[2]));
@@ -125,7 +125,7 @@
   /* For ARMv8-A we can use an LDAEXD to atomically load two 32-bit registers
      when acquire or stronger semantics are needed.  When the relaxed model is
      used this can be relaxed to a normal LDRD.  */
-  if (TARGET_HAVE_LDACQ)
+  if (TARGET_HAVE_LDACQEXD)
     {
       if (is_mm_relaxed (model))
 	emit_insn (gen_arm_atomic_loaddi2_ldrd (operands[0], operands[1]));
@@ -436,7 +436,7 @@
 	(unspec_volatile:DI
 	  [(match_operand:DI 1 "mem_noofs_operand" "Ua")]
 	  VUNSPEC_LAX))]
-  "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
+  "TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"
   "ldaexd%?\t%0, %H0, %C1"
   [(set_attr "predicable" "yes")
    (set_attr "predicable_short_it" "no")])
@@ -472,7 +472,7 @@
 	(unspec_volatile:DI
 	  [(match_operand:DI 2 "s_register_operand" "r")]
 	  VUNSPEC_SLX))]
-  "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
+  "TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"
   {
     /* See comment in arm_store_exclusive<mode> above.  */
     gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);