sh.h (TARGET_SH4): Remove and use default implementation.

gcc/
	* config/sh/sh.h (TARGET_SH4): Remove and use default implementation.
	(TARGET_FPU_DOUBLE): Simplify.
	(BASE_ARG_REG, DOUBLE_TYPE_SIZE, OPTIMIZE_MODE_SWITCHING): Replace
	'TARGET_SH4 || TARGET_SH2A_DOUBLE' conditions with 'TARGET_FPU_DOUBLE'.
	* config/sh/sh.c: Replace 'TARGET_SH4 || TARGET_SH2A_DOUBLE' conditions
	with 'TARGET_FPU_DOUBLE'.
	* config/sh/sh.md: Likewise.

From-SVN: r235689

3 files changed, 59 insertions, 69 deletions

diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index b37d3ab..cddb31c 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -6821,7 +6821,7 @@ push (int rn)
     x = gen_push_fpul ();
   else if (rn == FPSCR_REG)
     x = gen_push_fpscr ();
-  else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD
+  else if (TARGET_FPU_DOUBLE && TARGET_FMOVD
 	   && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn))
     {
       if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
@@ -6847,7 +6847,7 @@ pop (int rn)
     x = gen_pop_fpul ();
   else if (rn == FPSCR_REG)
     x = gen_pop_fpscr ();
-  else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD
+  else if (TARGET_FPU_DOUBLE && TARGET_FMOVD
 	   && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn))
     {
       if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
@@ -6991,12 +6991,11 @@ calc_live_regs (HARD_REG_SET *live_regs_mask)
   nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
 
   CLEAR_HARD_REG_SET (*live_regs_mask);
-  if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD && interrupt_handler
+  if (TARGET_FPU_DOUBLE && TARGET_FMOVD && interrupt_handler
       && df_regs_ever_live_p (FPSCR_REG))
     target_flags &= ~MASK_FPU_SINGLE;
   /* If we can save a lot of saves by switching to double mode, do that.  */
-  else if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD
-	   && TARGET_FPU_SINGLE)
+  else if (TARGET_FPU_DOUBLE && TARGET_FMOVD && TARGET_FPU_SINGLE)
     for (count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
       if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
 	  && (! call_really_used_regs[reg]
@@ -7058,7 +7057,7 @@ calc_live_regs (HARD_REG_SET *live_regs_mask)
 	  SET_HARD_REG_BIT (*live_regs_mask, reg);
 	  count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
 
-	  if ((TARGET_SH4 || TARGET_SH2A_DOUBLE) && TARGET_FMOVD
+	  if (TARGET_FPU_DOUBLE && TARGET_FMOVD
 	      && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
 	    {
 	      if (FP_REGISTER_P (reg))
@@ -7543,7 +7542,7 @@ sh_builtin_saveregs (void)
   fpregs = copy_to_mode_reg (Pmode,
 			     plus_constant (Pmode, XEXP (regbuf, 0),
 					    n_floatregs * UNITS_PER_WORD));
-  if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
+  if (TARGET_FPU_DOUBLE)
     {
       rtx mem;
       for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
@@ -7796,7 +7795,7 @@ sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
 	    }
 	}
 
-      if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
+      if (TARGET_FPU_DOUBLE)
 	{
 	  pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
 			   || (TREE_CODE (eff_type) == COMPLEX_TYPE
@@ -8020,7 +8019,7 @@ sh_round_reg (const CUMULATIVE_ARGS& cum, machine_mode mode)
      function as is.  Make this more readable.  */
   return
   (((TARGET_ALIGN_DOUBLE
-      || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
+      || (TARGET_FPU_DOUBLE
 	  && (mode == DFmode || mode == DCmode)
 	  && cum.arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (mode)))
      && GET_MODE_UNIT_SIZE (mode) > UNITS_PER_WORD)
@@ -8065,7 +8064,7 @@ sh_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
   int words = 0;
 
   if (sh_pass_in_reg_p (*cum, mode, type)
-      && !(TARGET_SH4 || TARGET_SH2A_DOUBLE)
+      && !TARGET_FPU_DOUBLE
       && (sh_round_reg (*cum, mode)
 	  + (mode != BLKmode
 	     ? CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD)
@@ -9187,8 +9186,7 @@ sh_legitimate_address_p (machine_mode mode, rtx x, bool strict)
 	return true;
 
       if (GET_MODE_SIZE (mode) <= 4
-	  || ((TARGET_SH4 || TARGET_SH2A_DOUBLE)
-	      && TARGET_FMOVD && mode == DFmode))
+	  || (TARGET_FPU_DOUBLE && TARGET_FMOVD && mode == DFmode))
 	{
 	  if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
 	      && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
@@ -9373,7 +9371,7 @@ sh_legitimize_address (rtx x, rtx oldx, machine_mode mode)
   if (flag_pic)
     x = legitimize_pic_address (oldx, mode, NULL_RTX);
 
-  if (((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
+  if ((TARGET_FPU_DOUBLE && mode == DFmode)
       || (TARGET_SH2E && mode == SFmode))
     return x;
 
@@ -10732,8 +10730,7 @@ sh_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
       if (mode == SFmode
 	  || mode == SImode
 	  || ((TARGET_SH2E) && mode == SCmode)
-	  || ((((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
-	       || mode == DCmode)
+	  || (((TARGET_FPU_DOUBLE && mode == DFmode) || mode == DCmode)
 	      && ((regno - FIRST_FP_REG) & 1) == 0)
 	  || (TARGET_SH4 && mode == TImode
 	      && ((regno - FIRST_FP_REG) & 3) == 0))
@@ -11558,7 +11555,7 @@ static bool
 sh_legitimize_address_displacement (rtx *disp, rtx *offs,
 				    machine_mode mode)
 {
-  if (((TARGET_SH4 || TARGET_SH2A_DOUBLE) && mode == DFmode)
+  if ((TARGET_FPU_DOUBLE && mode == DFmode)
       || (TARGET_SH2E && mode == SFmode))
     return false;
 
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 719ebd3..60c6250 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -60,16 +60,11 @@ extern int code_for_indirect_jump_scratch;
 #define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A)
 
 /* Nonzero if a double-precision FPU is available.  */
-#define TARGET_FPU_DOUBLE \
-  ((target_flags & MASK_SH4) != 0 || TARGET_SH2A_DOUBLE)
+#define TARGET_FPU_DOUBLE (TARGET_SH4 || TARGET_SH2A_DOUBLE)
 
 /* Nonzero if an FPU is available.  */
 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE)
 
-/* Nonzero if we should generate code using type 4 insns.  */
-#undef TARGET_SH4
-#define TARGET_SH4 ((target_flags & MASK_SH4) != 0 && TARGET_SH1)
-
 /* Nonzero if we're generating code for SH4a, unless the use of the
    FPU is disabled (which makes it compatible with SH4al-dsp).  */
 #define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY)
@@ -1085,7 +1080,7 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
 #define NPARM_REGS(MODE) \
   (TARGET_FPU_ANY && (MODE) == SFmode \
    ? 8 \
-   : (TARGET_SH4 || TARGET_SH2A_DOUBLE) \
+   : TARGET_FPU_DOUBLE \
      && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
 	 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
    ? 8 \
@@ -1142,8 +1137,9 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
 #define BASE_ARG_REG(MODE) \
   ((TARGET_SH2E && ((MODE) == SFmode))			\
    ? FIRST_FP_PARM_REG					\
-   : (TARGET_SH4 || TARGET_SH2A_DOUBLE) && (GET_MODE_CLASS (MODE) == MODE_FLOAT	\
-		    || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
+   : TARGET_FPU_DOUBLE					\
+     && (GET_MODE_CLASS (MODE) == MODE_FLOAT		\
+	 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\
    ? FIRST_FP_PARM_REG					\
    : FIRST_PARM_REG)
 
@@ -1487,8 +1483,7 @@ struct sh_args {
 
 /* Since the SH2e has only `float' support, it is desirable to make all
    floating point types equivalent to `float'.  */
-#define DOUBLE_TYPE_SIZE ((TARGET_SH2E && ! TARGET_SH4 && ! TARGET_SH2A_DOUBLE)\
-			  ? 32 : 64)
+#define DOUBLE_TYPE_SIZE (TARGET_FPU_SINGLE_ONLY ? 32 : 64)
 
 /* 'char' is signed by default.  */
 #define DEFAULT_SIGNED_CHAR  1
@@ -1886,7 +1881,7 @@ extern int current_function_interrupt;
 
 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE }
 
-#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_SH4 || TARGET_SH2A_DOUBLE)
+#define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_FPU_DOUBLE)
 
 #define ACTUAL_NORMAL_MODE(ENTITY) \
   (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE)
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index f019d40..3af9644 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -2256,8 +2256,7 @@
    (clobber (reg:SI R5_REG))
    (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
    (use (match_operand 2 "" "Z,Ccl"))]
-  "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE)
-   && TARGET_FPU_SINGLE"
+  "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
   "@
 	jsr	@%1%#
 	bsrf	%1\n%O2:%#"
@@ -2393,8 +2392,7 @@
    (clobber (reg:SI R2_REG))
    (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
    (use (match_operand 2 "" "Z,Ccl"))]
-  "(TARGET_FPU_SINGLE_ONLY || TARGET_FPU_DOUBLE)
-   && TARGET_FPU_SINGLE"
+  "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
   "@
 	jsr	@%1%#
 	bsrf	%1\n%O2:%#"
@@ -5568,7 +5566,7 @@
   [(set (match_operand:DF 0 "general_movdst_operand" "=r,r,r,m")
 	(match_operand:DF 1 "general_movsrc_operand" "r,FQ,m,r"))]
   "TARGET_SH1
-   && (! (TARGET_SH4 || TARGET_SH2A_DOUBLE) || reload_completed
+   && (!TARGET_FPU_DOUBLE || reload_completed
        /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
        || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
        || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
@@ -5591,7 +5589,7 @@
 	(match_operand:DF 1 "general_movsrc_operand"  "d,r,F,m,d,FQ,m,r,d,r"))
    (use (reg:SI FPSCR_MODES_REG))
    (clobber (match_scratch:SI 2                      "=X,X,&z,X,X,X,X,X,X,X"))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
+  "TARGET_FPU_DOUBLE
    && (arith_reg_operand (operands[0], DFmode)
        || arith_reg_operand (operands[1], DFmode))"
   {
@@ -5641,7 +5639,7 @@
 	(match_operand:DF 1 "register_operand"))
    (use (reg:SI FPSCR_MODES_REG))
    (clobber (match_scratch:SI 2))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed
+  "TARGET_FPU_DOUBLE && reload_completed
    && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
   [(const_int 0)]
 {
@@ -5665,7 +5663,7 @@
 	(match_operand:DF 1 "general_movsrc_operand"  ""))
    (use (reg:SI FPSCR_MODES_REG))
    (clobber (match_scratch:SI 2))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)
+  "TARGET_FPU_DOUBLE
    && reload_completed
    && true_regnum (operands[0]) < 16
    && true_regnum (operands[1]) < 16"
@@ -5736,7 +5734,7 @@
 	(match_operand:DF 1 "memory_operand"  ""))
    (use (reg:SI FPSCR_MODES_REG))
    (clobber (reg:SI R0_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && reload_completed"
+  "TARGET_FPU_DOUBLE && reload_completed"
   [(parallel [(set (match_dup 0) (match_dup 1))
 	      (use (reg:SI FPSCR_MODES_REG))
 	      (clobber (scratch:SI))])]
@@ -5792,7 +5790,7 @@
 	(mem:DF (match_operand:SI 1 "register_operand" "")))
    (use (reg:SI FPSCR_MODES_REG))
    (clobber (match_scratch:SI 2))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
+  "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
    && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
    && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
   [(const_int 0)]
@@ -5817,7 +5815,7 @@
 	(match_operand:DF 1 "memory_operand" ""))
    (use (reg:SI FPSCR_MODES_REG))
    (clobber (match_scratch:SI 2))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
+  "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
    && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
   [(const_int 0)]
 {
@@ -5884,7 +5882,7 @@
 	(match_operand:DF 1 "register_operand" ""))
    (use (reg:SI FPSCR_MODES_REG))
    (clobber (match_scratch:SI 2))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE) && ! TARGET_FMOVD && reload_completed
+  "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
    && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
   [(const_int 0)]
 {
@@ -6010,7 +6008,7 @@
   ""
 {
   prepare_move_operands (operands, DFmode);
-  if (TARGET_SH4 || TARGET_SH2A_DOUBLE)
+  if (TARGET_FPU_DOUBLE)
     {
       emit_insn (gen_movdf_i4 (operands[0], operands[1]));
       DONE;
@@ -8563,7 +8561,7 @@
 	(match_operator:SI 1 "ordered_comparison_operator"
 	 [(match_operand:DF 2 "arith_operand" "")
 	  (match_operand:DF 3 "arith_operand" "")]))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE"
+  "TARGET_FPU_DOUBLE"
 {
   if (! currently_expanding_to_rtl)
     FAIL;
@@ -9143,7 +9141,7 @@
 	(xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_SZ)))
    (set (reg:SI FPSCR_MODES_REG)
 	(unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fschg"
   [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
 
@@ -9493,7 +9491,7 @@
   [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
 	(plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
 		 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE"
+  "TARGET_FPU_DOUBLE"
 {
   emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2]));
   DONE;
@@ -9505,7 +9503,7 @@
 		 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fadd	%2,%0"
   [(set_attr "type" "dfp_arith")
    (set_attr "fp_mode" "double")])
@@ -9514,7 +9512,7 @@
   [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
 	(minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
 		  (match_operand:DF 2 "fp_arith_reg_operand" "")))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE"
+  "TARGET_FPU_DOUBLE"
 {
   emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2]));
   DONE;
@@ -9526,7 +9524,7 @@
 		  (match_operand:DF 2 "fp_arith_reg_operand" "f")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fsub	%2,%0"
   [(set_attr "type" "dfp_arith")
    (set_attr "fp_mode" "double")])
@@ -9535,7 +9533,7 @@
   [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
 	(mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
 		 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE"
+  "TARGET_FPU_DOUBLE"
 {
   emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2]));
   DONE;
@@ -9547,7 +9545,7 @@
 		 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fmul	%2,%0"
   [(set_attr "type" "dfp_mul")
    (set_attr "fp_mode" "double")])
@@ -9556,7 +9554,7 @@
   [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
 	(div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
 		(match_operand:DF 2 "fp_arith_reg_operand" "")))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE"
+  "TARGET_FPU_DOUBLE"
 {
   emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2]));
   DONE;
@@ -9568,7 +9566,7 @@
 		(match_operand:DF 2 "fp_arith_reg_operand" "f")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fdiv	%2,%0"
   [(set_attr "type" "dfdiv")
    (set_attr "fp_mode" "double")])
@@ -9576,7 +9574,7 @@
 (define_expand "floatsidf2"
   [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
 	(float:DF (match_operand:SI 1 "fpul_operand" "")))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE"
+  "TARGET_FPU_DOUBLE"
 {
   emit_insn (gen_floatsidf2_i (operands[0], operands[1]));
   DONE;
@@ -9587,7 +9585,7 @@
 	(float:DF (match_operand:SI 1 "fpul_operand" "y")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "float	%1,%0"
   [(set_attr "type" "dfp_conv")
    (set_attr "fp_mode" "double")])
@@ -9595,7 +9593,7 @@
 (define_expand "fix_truncdfsi2"
   [(set (match_operand:SI 0 "fpul_operand" "")
 	(fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE"
+  "TARGET_FPU_DOUBLE"
 {
    emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1]));
    DONE;
@@ -9606,7 +9604,7 @@
 	(fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "ftrc	%1,%0"
   [(set_attr "type" "dfp_conv")
    (set_attr "dfp_comp" "no")
@@ -9618,7 +9616,7 @@
 	       (match_operand:DF 1 "fp_arith_reg_operand" "f")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fcmp/gt	%1,%0"
   [(set_attr "type" "dfp_cmp")
    (set_attr "fp_mode" "double")])
@@ -9629,7 +9627,7 @@
 	       (match_operand:DF 1 "fp_arith_reg_operand" "f")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fcmp/eq	%1,%0"
   [(set_attr "type" "dfp_cmp")
    (set_attr "fp_mode" "double")])
@@ -9641,7 +9639,7 @@
 		       (match_operand:DF 1 "fp_arith_reg_operand" "f"))))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "TARGET_IEEE && (TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_IEEE && TARGET_FPU_DOUBLE"
 {
   return output_ieee_ccmpeq (insn, operands);
 }
@@ -9655,7 +9653,7 @@
 			(match_operand:DF 2 "arith_operand" "")])
 		      (match_operand 3 "" "")
 		      (pc)))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE"
+  "TARGET_FPU_DOUBLE"
 {
   sh_emit_compare_and_branch (operands, DFmode);
   DONE;
@@ -9664,19 +9662,19 @@
 (define_expand "negdf2"
   [(set (match_operand:DF 0 "fp_arith_reg_operand")
 	(neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE")
+  "TARGET_FPU_DOUBLE")
 
 (define_insn "*negdf2_i"
   [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
 	(neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fneg	%0"
   [(set_attr "type" "fmove")])
 
 (define_expand "sqrtdf2"
   [(set (match_operand:DF 0 "fp_arith_reg_operand")
 	(sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE"
+  "TARGET_FPU_DOUBLE"
 {
   emit_insn (gen_sqrtdf2_i (operands[0], operands[1]));
   DONE;
@@ -9687,7 +9685,7 @@
 	(sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fsqrt	%0"
   [(set_attr "type" "dfdiv")
    (set_attr "fp_mode" "double")])
@@ -9695,19 +9693,19 @@
 (define_expand "absdf2"
   [(set (match_operand:DF 0 "fp_arith_reg_operand")
 	(abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE")
+  "TARGET_FPU_DOUBLE")
 
 (define_insn "*absdf2_i"
   [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
 	(abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fabs	%0"
   [(set_attr "type" "fmove")])
 
 (define_expand "extendsfdf2"
   [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
 	(float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE"
+  "TARGET_FPU_DOUBLE"
 {
   emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1]));
   DONE;
@@ -9718,7 +9716,7 @@
 	(float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fcnvsd  %1,%0"
   [(set_attr "type" "fp")
    (set_attr "fp_mode" "double")])
@@ -9726,7 +9724,7 @@
 (define_expand "truncdfsf2"
   [(set (match_operand:SF 0 "fpul_operand" "")
 	(float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
-  "TARGET_SH4 || TARGET_SH2A_DOUBLE"
+  "TARGET_FPU_DOUBLE"
 {
   emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1]));
   DONE;
@@ -9737,7 +9735,7 @@
 	(float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
    (clobber (reg:SI FPSCR_STAT_REG))
    (use (reg:SI FPSCR_MODES_REG))]
-  "(TARGET_SH4 || TARGET_SH2A_DOUBLE)"
+  "TARGET_FPU_DOUBLE"
   "fcnvds  %1,%0"
   [(set_attr "type" "fp")
    (set_attr "fp_mode" "double")])