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authorAndrew Pinski <apinski@marvell.com>2022-01-09 23:39:31 -0800
committerAndrew Pinski <apinski@marvell.com>2022-01-23 22:17:59 +0000
commitcbcf4a50fa21abd7a4a50a7ce47ada80b115febc (patch)
treeb12e35dc952601d083fbb9ece21f2ad46802fd85 /gcc/config
parent603a9ab41f4fd2748407fecf8b4ce2e5f9f71c23 (diff)
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[aarch64/64821]: Simplify __builtin_aarch64_sqrt* into internal function .SQRT.
This is a simple patch which simplifies the __builtin_aarch64_sqrt* builtins into the internal function SQRT which allows for constant folding and other optimizations at the gimple level. It was originally suggested we do to __builtin_sqrt just for __builtin_aarch64_sqrtdf when -fno-math-errno but since r6-4969-g686ee9719a4 we have the internal function SQRT which does the same so it makes we don't need to check -fno-math-errno either now. Applied as approved after bootstrapped and tested on aarch64-linux-gnu with no regressions. PR target/64821 gcc/ChangeLog: * config/aarch64/aarch64-builtins.cc (aarch64_general_gimple_fold_builtin): Handle __builtin_aarch64_sqrt* and simplify into SQRT internal function. gcc/testsuite/ChangeLog: * gcc.target/aarch64/vsqrt-1.c: New test. * gcc.target/aarch64/vsqrt-2.c: New test.
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/aarch64/aarch64-builtins.cc7
1 files changed, 7 insertions, 0 deletions
diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc
index b7f338d..5217dbd 100644
--- a/gcc/config/aarch64/aarch64-builtins.cc
+++ b/gcc/config/aarch64/aarch64-builtins.cc
@@ -2820,6 +2820,13 @@ aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt,
gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt));
break;
+ /* Lower sqrt builtins to gimple/internal function sqrt. */
+ BUILTIN_VHSDF_DF (UNOP, sqrt, 2, FP)
+ new_stmt = gimple_build_call_internal (IFN_SQRT,
+ 1, args[0]);
+ gimple_call_set_lhs (new_stmt, gimple_call_lhs (stmt));
+ break;
+
/*lower store and load neon builtins to gimple. */
BUILTIN_VALL_F16 (LOAD1, ld1, 0, LOAD)
BUILTIN_VDQ_I (LOAD1_U, ld1, 0, LOAD)