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| author | Bernd Schmidt <bernds@codesourcery.com> | 2010-09-21 13:11:03 +0000 |
|---|---|---|
| committer | Bernd Schmidt <bernds@gcc.gnu.org> | 2010-09-21 13:11:03 +0000 |
| commit | c9cdcaa5905985e8c97e3cbb0d9c6db3ab707910 (patch) | |
| tree | 6797cdad122cb3677f30fa839ae88b82931ab1f3 /gcc/config | |
| parent | 903c31ee41c1a086b30f17f2c58aa1bcd85028d7 (diff) | |
| download | gcc-c9cdcaa5905985e8c97e3cbb0d9c6db3ab707910.zip gcc-c9cdcaa5905985e8c97e3cbb0d9c6db3ab707910.tar.gz gcc-c9cdcaa5905985e8c97e3cbb0d9c6db3ab707910.tar.bz2 | |
iterators.md (qhs_extenddi_op): New mode_attr.
* config/arm/iterators.md (qhs_extenddi_op): New mode_attr.
(qhs_extenddi_cstr): Likewise.
* config/arm/arm.md (zero_extend<mode>di2, extend<mode>di2): Use
them for the source operand.
From-SVN: r164477
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/arm/arm.md | 6 | ||||
| -rw-r--r-- | gcc/config/arm/iterators.md | 4 |
2 files changed, 8 insertions, 2 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 47be462..c54bb2a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4042,7 +4042,8 @@ (define_insn "zero_extend<mode>di2" [(set (match_operand:DI 0 "s_register_operand" "=r") - (zero_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))] + (zero_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>" + "<qhs_extenddi_cstr>")))] "TARGET_32BIT <qhs_zextenddi_cond>" "#" [(set_attr "length" "8") @@ -4052,7 +4053,8 @@ (define_insn "extend<mode>di2" [(set (match_operand:DI 0 "s_register_operand" "=r") - (sign_extend:DI (match_operand:QHSI 1 "nonimmediate_operand" "rm")))] + (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>" + "<qhs_extenddi_cstr>")))] "TARGET_32BIT <qhs_sextenddi_cond>" "#" [(set_attr "length" "8") diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 8e9f100..887c962b 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -381,6 +381,10 @@ (define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")]) (define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "&& arm_arch6")]) +(define_mode_attr qhs_extenddi_op [(SI "s_register_operand") + (HI "nonimmediate_operand") + (QI "nonimmediate_operand")]) +(define_mode_attr qhs_extenddi_cstr [(SI "r") (HI "rm") (QI "rm")]) ;;---------------------------------------------------------------------------- ;; Code attributes |