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| author | Uros Bizjak <ubizjak@gmail.com> | 2018-11-16 17:42:16 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2018-11-16 17:42:16 +0100 |
| commit | b41835733bc337580a0de6b8ba5de4b00d391fc6 (patch) | |
| tree | e1bf549d8dd8f611bba780a736549881074eb90d /gcc/config | |
| parent | 258b3854633d78954f9f9aba5cc433c992a5010e (diff) | |
| download | gcc-b41835733bc337580a0de6b8ba5de4b00d391fc6.zip gcc-b41835733bc337580a0de6b8ba5de4b00d391fc6.tar.gz gcc-b41835733bc337580a0de6b8ba5de4b00d391fc6.tar.bz2 | |
re PR target/88051 (internal compiler error: in add_clobbers, at config/i386/sync.md:1762)
PR target/88051
* config/i386/i386.md (floatunsdidf2): Allow only 64bit AVX512F targets.
* config/i386/sse.md (UNSPEC_MOVDI_TO_SSE): New UNSPEC.
(movdi_to_sse): Rewrite using UNSPEC_MOVDI_TO_SSE unspec.
From-SVN: r266218
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.md | 3 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 11 |
2 files changed, 9 insertions, 5 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 9c359c0..1a3a179 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -5194,7 +5194,8 @@ [(set (match_operand:DF 0 "register_operand") (unsigned_float:DF (match_operand:DI 1 "nonimmediate_operand")))] - "(TARGET_KEEPS_VECTOR_ALIGNED_STACK || TARGET_AVX512F) + "((TARGET_64BIT && TARGET_AVX512F) + || TARGET_KEEPS_VECTOR_ALIGNED_STACK) && TARGET_SSE2 && TARGET_SSE_MATH" { if (!TARGET_64BIT) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5020c05..18685de 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -21,6 +21,9 @@ ;; SSE UNSPEC_MOVNT + ;; SSE2 + UNSPEC_MOVDI_TO_SSE + ;; SSE3 UNSPEC_LDDQU @@ -1235,10 +1238,10 @@ ;; from there. (define_insn_and_split "movdi_to_sse" - [(parallel - [(set (match_operand:V4SI 0 "register_operand" "=?x,x") - (subreg:V4SI (match_operand:DI 1 "nonimmediate_operand" "r,m") 0)) - (clobber (match_scratch:V4SI 2 "=&x,X"))])] + [(set (match_operand:V4SI 0 "register_operand" "=?x,x") + (unspec:V4SI [(match_operand:DI 1 "nonimmediate_operand" "r,m")] + UNSPEC_MOVDI_TO_SSE)) + (clobber (match_scratch:V4SI 2 "=&x,X"))] "!TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES_TO_VEC" "#" "&& reload_completed" |