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| author | Devang Patel <dpatel@apple.com> | 2005-06-17 13:30:42 -0700 |
|---|---|---|
| committer | Devang Patel <dpatel@gcc.gnu.org> | 2005-06-17 13:30:42 -0700 |
| commit | afca671b7852829464044338e7a3c0a7353a39e9 (patch) | |
| tree | 6d7b0c59ce1ab4e41f91ce50479623e2ccf8f8ae /gcc/config | |
| parent | 599c25e213782e397e5bc16f942ffae0425f6fab (diff) | |
| download | gcc-afca671b7852829464044338e7a3c0a7353a39e9.zip gcc-afca671b7852829464044338e7a3c0a7353a39e9.tar.gz gcc-afca671b7852829464044338e7a3c0a7353a39e9.tar.bz2 | |
predicates.md (s5bit_cint_operand, [...]): New.
* config/rs6000/predicates.md (s5bit_cint_operand,
u5bit_cint_operand): New.
* config/rs6000/altivec.md (altivec_vspltb, altivec_vsplth,
altivec_vspltisw_v4sf): Use new 5 bit constant operand predicates.
* config/rs6000/rs6000.c (rs6000_expand_unop_builtin): Fix signed
5 bit constant check.
From-SVN: r101133
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 10 | ||||
| -rw-r--r-- | gcc/config/rs6000/predicates.md | 10 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 4 |
3 files changed, 17 insertions, 7 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 418228d..847812d 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1167,7 +1167,7 @@ (vec_duplicate:V16QI (vec_select:QI (match_operand:V16QI 1 "register_operand" "v") (parallel - [(match_operand:QI 2 "immediate_operand" "i")]))))] + [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] "TARGET_ALTIVEC" "vspltb %0,%1,%2" [(set_attr "type" "vecperm")]) @@ -1177,7 +1177,7 @@ (vec_duplicate:V8HI (vec_select:HI (match_operand:V8HI 1 "register_operand" "v") (parallel - [(match_operand:QI 2 "immediate_operand" "i")]))))] + [(match_operand:QI 2 "u5bit_cint_operand" "")]))))] "TARGET_ALTIVEC" "vsplth %0,%1,%2" [(set_attr "type" "vecperm")]) @@ -1187,7 +1187,7 @@ (vec_duplicate:V4SI (vec_select:SI (match_operand:V4SI 1 "register_operand" "v") (parallel - [(match_operand:QI 2 "immediate_operand" "i")]))))] + [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))] "TARGET_ALTIVEC" "vspltw %0,%1,%2" [(set_attr "type" "vecperm")]) @@ -1195,7 +1195,7 @@ (define_insn "altivec_vspltis<VI_char>" [(set (match_operand:VI 0 "register_operand" "=v") (vec_duplicate:VI - (match_operand:QI 1 "const_int_operand" "i")))] + (match_operand:QI 1 "s5bit_cint_operand" "i")))] "TARGET_ALTIVEC" "vspltis<VI_char> %0,%1" [(set_attr "type" "vecperm")]) @@ -1203,7 +1203,7 @@ (define_insn "altivec_vspltisw_v4sf" [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_duplicate:V4SF - (float:SF (match_operand:QI 1 "const_int_operand" "i"))))] + (float:SF (match_operand:QI 1 "s5bit_cint_operand" "i"))))] "TARGET_ALTIVEC" "vspltisw %0,%1" [(set_attr "type" "vecperm")]) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 664c7f0..a89b10c 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -44,6 +44,16 @@ (and (match_code "reg") (match_test "XER_REGNO_P (REGNO (op))"))) +;; Return 1 if op is a signed 5-bit constant integer. +(define_predicate "s5bit_cint_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15"))) + +;; Return 1 if op is a unsigned 5-bit constant integer. +(define_predicate "u5bit_cint_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31"))) + ;; Return 1 if op is a signed 8-bit constant integer. ;; Integer multiplcation complete more quickly (define_predicate "s8bit_cint_operand" diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index db7f851..cf54321 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6241,8 +6241,8 @@ rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target) { /* Only allow 5-bit *signed* literals. */ if (GET_CODE (op0) != CONST_INT - || INTVAL (op0) > 0x1f - || INTVAL (op0) < -0x1f) + || INTVAL (op0) > 15 + || INTVAL (op0) < -16) { error ("argument 1 must be a 5-bit signed literal"); return const0_rtx; |