Fix spelling errors.

From-SVN: r10289

20 files changed, 29 insertions, 29 deletions

diff --git a/gcc/config/1750a/1750a.h b/gcc/config/1750a/1750a.h
index f70c665..d0bac46 100644
--- a/gcc/config/1750a/1750a.h
+++ b/gcc/config/1750a/1750a.h
@@ -519,7 +519,7 @@ enum reg_class { NO_REGS, INDEX_REGS, BASE_REGS, ALL_REGS, LIM_REG_CLASSES };
 /* Define the following macro if function calls on the target machine
    do not preserve any registers; in other words, if `CALL_USED_REGISTERS'
    has 1 for all registers. This macro enables `-fcaller-saves' by
-   default. Eventually that option will be nabled by default on all
+   default. Eventually that option will be enabled by default on all
    machines and both the option and this macro will be eliminated. */
 
 #define DEFAULT_CALLER_SAVES
diff --git a/gcc/config/1750a/1750a.md b/gcc/config/1750a/1750a.md
index 2032e23..02e6469 100644
--- a/gcc/config/1750a/1750a.md
+++ b/gcc/config/1750a/1750a.md
@@ -969,7 +969,7 @@
 ;********************
 
 ;; Bit field instructions, general cases.
-;; "o,d" constraint causes a nonoffsetable memref to match the "o"
+;; "o,d" constraint causes a nonoffsettable memref to match the "o"
 ;; so that its address is reloaded.
 
 ;; (define_insn "extv" ...
diff --git a/gcc/config/alpha/alpha.h b/gcc/config/alpha/alpha.h
index e3d0c86..3db24d5 100644
--- a/gcc/config/alpha/alpha.h
+++ b/gcc/config/alpha/alpha.h
@@ -1526,7 +1526,7 @@ extern char *current_function_name;
 /* Define an extra section for read-only data, a routine to enter it, and
    indicate that it is for read-only data.
 
-   The first timem we enter the readonly data sectiono for a file, we write
+   The first time we enter the readonly data section for a file, we write
    eight bytes of zero.  This works around a bug in DEC's assembler in
    some versions of OSF/1 V3.x.  */
 
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 3cfc238..db5ffde 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -780,7 +780,7 @@ enum reg_class
    Frame pointer elimination is automatically handled.
 
    All eliminations are permissible.  Note that ARG_POINTER_REGNUM and
-   HARD_FRAME_POINTER_REGNUM are infact the same thing.  If we need a frame
+   HARD_FRAME_POINTER_REGNUM are in fact the same thing.  If we need a frame
    pointer, we must eliminate FRAME_POINTER_REGNUM into
    HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM.  */
 #define CAN_ELIMINATE(FROM, TO)		\
diff --git a/gcc/config/dsp16xx/dsp16xx.h b/gcc/config/dsp16xx/dsp16xx.h
index ae2ec64..6e32594 100644
--- a/gcc/config/dsp16xx/dsp16xx.h
+++ b/gcc/config/dsp16xx/dsp16xx.h
@@ -1007,7 +1007,7 @@ enum reg_class
 #endif
 
 /* A C expression for the maximum number of consecutive registers of class CLASS
-   needed to hold a vlaue of mode MODE */
+   needed to hold a value of mode MODE */
 #define CLASS_MAX_NREGS(CLASS, MODE)                                \
     class_max_nregs(CLASS, MODE)
 
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index 03622ea..8db3c36 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -1,5 +1,5 @@
 /* Subroutines for insn-output.c for Hitachi H8/300.
-   Copyright (C) 1992, 1993, 1994 Free Software Foundation, Inc.
+   Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
    Contributed by Steve Chamberlain (sac@cygnus.com),
    Jim Wilson (wilson@cygnus.com), and Doug Evans (dje@cygnus.com).
 
@@ -2002,7 +2002,7 @@ fix_bit_operand (operands, what, type)
      char what;
      enum rtx_code type;
 {
-  /* The bit_operand predicate accepts any memory durint RTL generation, but
+  /* The bit_operand predicate accepts any memory during RTL generation, but
      only 'U' memory afterwards, so if this is a MEM operand, we must force
      it to be valid for 'U' by reloading the address.  */
 
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 1754bb0..6ad8616 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -1853,7 +1853,7 @@
   if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) >= 8)
     FAIL;
 
-  /* The bit_operand predicate accepts any memory durint RTL generation, but
+  /* The bit_operand predicate accepts any memory during RTL generation, but
      only 'U' memory afterwards, so if this is a MEM operand, we must force
      it to be valid for 'U' by reloading the address.  */
 
@@ -1897,7 +1897,7 @@
   if (INTVAL (operands[2]) != 1)
     FAIL;
 
-  /* The bit_operand predicate accepts any memory durint RTL generation, but
+  /* The bit_operand predicate accepts any memory during RTL generation, but
      only 'U' memory afterwards, so if this is a MEM operand, we must force
      it to be valid for 'U' by reloading the address.  */
 
diff --git a/gcc/config/i386/svr3dbx.h b/gcc/config/i386/svr3dbx.h
index 271c117..d3348d5 100644
--- a/gcc/config/i386/svr3dbx.h
+++ b/gcc/config/i386/svr3dbx.h
@@ -1,5 +1,5 @@
 /* Definitions for Intel 386 running system V, using dbx-in-coff encapsulation.
-   Copyright (C) 1992 Free Software Foundation, Inc.
+   Copyright (C) 1992, 1995 Free Software Foundation, Inc.
 
 This file is part of GNU CC.
 
@@ -37,7 +37,7 @@ Boston, MA 02111-1307, USA.  */
 
 /* With the current gas, .align N aligns to an N-byte boundary.
    This is done to be compatible with the system assembler.
-   You have specify -DOTHER_ALIGN wenn building gas-1.38.1. */
+   You must specify -DOTHER_ALIGN when building gas-1.38.1.  */
 
 #undef ASM_OUTPUT_ALIGN
 #define ASM_OUTPUT_ALIGN(FILE,LOG)	\
diff --git a/gcc/config/i960/i960.h b/gcc/config/i960/i960.h
index d14dd90..7bde093 100644
--- a/gcc/config/i960/i960.h
+++ b/gcc/config/i960/i960.h
@@ -308,7 +308,7 @@ extern int target_flags;
 /* Target machine storage layout.  */
 
 /* Define for cross-compilation from a host with a different float format
-   or endianess, as well as to support 80 bit long doubles on the i960.  */
+   or endianness, as well as to support 80 bit long doubles on the i960.  */
 #define REAL_ARITHMETIC
 
 /* Define this if most significant bit is lowest numbered
diff --git a/gcc/config/m68k/dpx2.h b/gcc/config/m68k/dpx2.h
index 94d7445..1402a25 100644
--- a/gcc/config/m68k/dpx2.h
+++ b/gcc/config/m68k/dpx2.h
@@ -1,6 +1,6 @@
 /* Definitions of target machine for GNU compiler.  
    Bull DPX/2 200 and 300 systems (m68k, SysVr3).
-   Copyright (C) 1987, 1993, 1994 Free Software Foundation, Inc.
+   Copyright (C) 1987, 1993, 1994, 1995 Free Software Foundation, Inc.
    Contributed by Frederic Pierresteguy (F.Pierresteguy@frcl.bull.fr).
 
 This file is part of GNU CC.
@@ -75,7 +75,7 @@ Boston, MA 02111-1307, USA.  */
  * handle the native MOTOROLA VERSAdos assembler.
  */
 
-/* See m68k.h.  3 means 68020 with 68881 and no bitfiled
+/* See m68k.h.  3 means 68020 with 68881 and no bitfield
  * bitfield instructions do not seem to work a clean way.
  */
 #undef TARGET_DEFAULT
diff --git a/gcc/config/m68k/m68kv4.h b/gcc/config/m68k/m68kv4.h
index 0af0013..4864413 100644
--- a/gcc/config/m68k/m68kv4.h
+++ b/gcc/config/m68k/m68kv4.h
@@ -209,7 +209,7 @@ do {									\
 #undef BIGGEST_ALIGNMENT
 #define BIGGEST_ALIGNMENT 64
 
-/* SVR4 m68k assembler is bitching on the `comm i,1,1' which askes for 
+/* SVR4 m68k assembler is bitching on the `comm i,1,1' which asks for 
    1 byte alignment. Don't generate alignment for COMMON seems to be
    safer until we the assembler is fixed. */
 #undef ASM_OUTPUT_ALIGNED_COMMON
diff --git a/gcc/config/m88k/m88k.md b/gcc/config/m88k/m88k.md
index 68d4181..9e58352 100644
--- a/gcc/config/m88k/m88k.md
+++ b/gcc/config/m88k/m88k.md
@@ -2717,7 +2717,7 @@
 
 ;;- multiply instructions
 ;;
-;; There is an unfounded silicon eratta for E.1 requiring that an
+;; There is an unfounded silicon errata for E.1 requiring that an
 ;; immediate constant value in div/divu/mul instructions be less than
 ;; 0x800.  This is no longer provided for.
 
@@ -2814,7 +2814,7 @@
 ;; negative.  The O/S will signal an overflow condition if the most
 ;; negative number (-214783648) is divided by negative 1.
 ;;
-;; There is an unfounded silicon eratta for E.1 requiring that an
+;; There is an unfounded silicon errata for E.1 requiring that an
 ;; immediate constant value in div/divu/mul instructions be less than
 ;; 0x800.  This is no longer provided for.
 
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index bab4e41..4e6d7f3 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -873,13 +873,13 @@ embedded_pic_offset (x)
 
       embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
       
-      /* Output code at function start to initialize the psuedo-reg.  */
+      /* Output code at function start to initialize the pseudo-reg.  */
       /* ??? We used to do this in FINALIZE_PIC, but that does not work for
 	 inline functions, because it is called after RTL for the function
 	 has been copied.  The pseudo-reg in embedded_pic_fnaddr_rtx however
 	 does not get copied, and ends up not matching the rest of the RTL.
 	 This solution works, but means that we get unnecessary code to
-	 initialize this value everytime a function is inlined into another
+	 initialize this value every time a function is inlined into another
 	 function.  */
       start_sequence ();
       emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 695c406..dfef30f 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -515,7 +515,7 @@ legitimize_pic_address (orig, mode, reg)
 {
   rtx pic_ref = orig;
 
-  /* Lables need special handling.  */
+  /* Labels need special handling.  */
   if (pic_label_operand (orig))
     {
       emit_insn (gen_pic_load_label (reg, orig));
diff --git a/gcc/config/pdp11/pdp11.h b/gcc/config/pdp11/pdp11.h
index ad3c622..46cd53d 100644
--- a/gcc/config/pdp11/pdp11.h
+++ b/gcc/config/pdp11/pdp11.h
@@ -566,7 +566,7 @@ maybe ac0 ? - as option someday! */
 /* should probably return DImode and DFmode in memory,lest
    we fill up all regs!
 
- have to, else we crash - exceptio: maybe return result in 
+ have to, else we crash - exception: maybe return result in 
  ac0 if DFmode and FPU present - compatibility problem with
  libraries for non-floating point ...
 */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 9bc64c3..e9ebfbf 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -862,8 +862,8 @@ typedef struct rs6000_stack {
   int push_p;			/* true if we need to allocate stack space */
   int calls_p;			/* true if the function makes any calls */
   int v4_call_p;		/* true if V.4 calling sequence used */
-  int gp_save_offset;		/* offset to save GP regs from inital SP */
-  int fp_save_offset;		/* offset to save FP regs from inital SP */
+  int gp_save_offset;		/* offset to save GP regs from initial SP */
+  int fp_save_offset;		/* offset to save FP regs from initial SP */
   int lr_save_offset;		/* offset to save LR from initial SP */
   int cr_save_offset;		/* offset to save CR from initial SP */
   int varargs_save_offset;	/* offset to save the varargs registers */
@@ -1279,7 +1279,7 @@ typedef struct rs6000_args
    For the RS/6000, if frame pointer elimination is being done, we would like
    to convert ap into fp, not sp.
 
-   We need r30 if -mmininal-toc was specified, and there are constant pool
+   We need r30 if -mminimal-toc was specified, and there are constant pool
    references.  */
 
 #define CAN_ELIMINATE(FROM, TO)					\
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index bb17943..70dd90d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3908,7 +3908,7 @@
     {
       /* If we are to limit the number of things we put in the TOC and
 	 this is a symbol plus a constant we can add in one insn,
-	 just put the sumbol in the TOC and add the constant.  Don't do
+	 just put the symbol in the TOC and add the constant.  Don't do
 	 this if reload is in progress.  */
       if (GET_CODE (operands[1]) == CONST
 	  && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
diff --git a/gcc/config/sh/lib1funcs.asm b/gcc/config/sh/lib1funcs.asm
index 1d5f811..6d8d3e8 100644
--- a/gcc/config/sh/lib1funcs.asm
+++ b/gcc/config/sh/lib1funcs.asm
@@ -1,4 +1,4 @@
-/* Copyright (C) 1994 Free Software Foundation, Inc.
+/* Copyright (C) 1994, 1995 Free Software Foundation, Inc.
 
 This file is free software; you can redistribute it and/or modify it
 under the terms of the GNU General Public License as published by the
@@ -779,7 +779,7 @@ ___mulsi3:
 	xtrct   r2,r3		! r3 = aacc
 	tst  	r3,r3		! msws zero ?
 	bf      hiset
-	rts			! yes - then weve got the answer
+	rts			! yes - then we have the answer
 	sts     macl,r0
 
 hiset:	sts	macl,r0		! r0 = bb*dd
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index dea9df9..59ed5fd 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -3959,7 +3959,7 @@ sparc_type_code (type)
   register unsigned long qualifiers = 0;
   register unsigned shift = 6;
 
-  /* Only the first 30 bits of the qualifer are valid.  We must refrain from
+  /* Only the first 30 bits of the qualifier are valid.  We must refrain from
      setting more, since some assemblers will give an error for this.  Also,
      we must be careful to avoid shifts of 32 bits or more to avoid getting
      unpredictable results.  */
diff --git a/gcc/config/winnt/spawnv.c b/gcc/config/winnt/spawnv.c
index 1b5ace1..bab753b 100644
--- a/gcc/config/winnt/spawnv.c
+++ b/gcc/config/winnt/spawnv.c
@@ -1,5 +1,5 @@
 /* This is a kludge to get around the Microsoft C spawn functions' propensity
-   to remove the outermost set of double quotes from all arguements.  */
+   to remove the outermost set of double quotes from all arguments.  */
 
 
 #define index(s,c) strchr((s),(c))