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| author | Adam Nemet <anemet@caviumnetworks.com> | 2008-09-26 23:38:20 +0000 |
|---|---|---|
| committer | Adam Nemet <nemet@gcc.gnu.org> | 2008-09-26 23:38:20 +0000 |
| commit | aa5409e7ade24c9972a5402c131d866ccba84ff4 (patch) | |
| tree | feaa8dbbf90b7217f8037ec462b991b2a33847de /gcc/config | |
| parent | 9c2b3df10a547f360f7ee8b0393f4b7fa3e5014b (diff) | |
| download | gcc-aa5409e7ade24c9972a5402c131d866ccba84ff4.zip gcc-aa5409e7ade24c9972a5402c131d866ccba84ff4.tar.gz gcc-aa5409e7ade24c9972a5402c131d866ccba84ff4.tar.bz2 | |
mips.h (ISA_HAS_DMUL3, [...]): Change them to yield false with MIPS16.
* config/mips/mips.h (ISA_HAS_DMUL3, ISA_HAS_BADDU, ISA_HAS_BBIT,
ISA_HAS_CINS, ISA_HAS_EXTS, ISA_HAS_SEQ_SNE, ISA_HAS_POP): Change
them to yield false with MIPS16.
From-SVN: r140714
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/mips/mips.h | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 55e240e..dc390df 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -783,7 +783,9 @@ enum mips_code_readable_setting { && !TARGET_MIPS16) /* ISA has a three-operand multiplication instruction. */ -#define ISA_HAS_DMUL3 (TARGET_64BIT && TARGET_OCTEON) +#define ISA_HAS_DMUL3 (TARGET_64BIT \ + && TARGET_OCTEON \ + && !TARGET_MIPS16) /* ISA has the floating-point conditional move instructions introduced in mips4. */ @@ -1011,22 +1013,22 @@ enum mips_code_readable_setting { : ISA_HAS_LL_SC) /* ISA includes the baddu instruction. */ -#define ISA_HAS_BADDU TARGET_OCTEON +#define ISA_HAS_BADDU (TARGET_OCTEON && !TARGET_MIPS16) /* ISA includes the bbit* instructions. */ -#define ISA_HAS_BBIT TARGET_OCTEON +#define ISA_HAS_BBIT (TARGET_OCTEON && !TARGET_MIPS16) /* ISA includes the cins instruction. */ -#define ISA_HAS_CINS TARGET_OCTEON +#define ISA_HAS_CINS (TARGET_OCTEON && !TARGET_MIPS16) /* ISA includes the exts instruction. */ -#define ISA_HAS_EXTS TARGET_OCTEON +#define ISA_HAS_EXTS (TARGET_OCTEON && !TARGET_MIPS16) /* ISA includes the seq and sne instructions. */ -#define ISA_HAS_SEQ_SNE TARGET_OCTEON +#define ISA_HAS_SEQ_SNE (TARGET_OCTEON && !TARGET_MIPS16) /* ISA includes the pop instruction. */ -#define ISA_HAS_POP TARGET_OCTEON +#define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) /* The CACHE instruction is available in non-MIPS16 code. */ #define TARGET_CACHE_BUILTIN (mips_isa >= 3) |