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authorJakub Jelinek <jakub@redhat.com>2016-02-12 00:53:54 +0100
committerJakub Jelinek <jakub@gcc.gnu.org>2016-02-12 00:53:54 +0100
commit9c58255170517b1b677ab0fac5cff46cc27c1dbd (patch)
treecde01d417194bbc82c2a04436bcde13a70a10e41 /gcc/config
parent66756373c1940650568173b6d9c32325429bfc34 (diff)
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cgraph.c: Spelling fixes - behaviour -> behavior and neighbour -> neighbor.
* cgraph.c: Spelling fixes - behaviour -> behavior and neighbour -> neighbor. * target.def: Likewise. * sel-sched.c: Likewise. * config/mips/mips.c: Likewise. * config/arc/arc.md: Likewise. * config/arm/cortex-a57.md: Likewise. * config/arm/arm.c: Likewise. * config/arm/neon.md: Likewise. * config/arm/arm-c.c: Likewise. * config/vms/vms-c.c: Likewise. * config/s390/s390.c: Likewise. * config/i386/znver1.md: Likewise. * config/i386/i386.c: Likewise. * config/ia64/hpux-unix2003.h: Likewise. * config/msp430/msp430.md: Likewise. * config/rx/rx.c: Likewise. * config/rx/rx.md: Likewise. * config/aarch64/aarch64-simd.md: Likewise. * config/aarch64/aarch64.c: Likewise. * config/nvptx/nvptx.c: Likewise. * config/bfin/bfin.c: Likewise. * config/cris/cris.opt: Likewise. * config/rs6000/rs6000.c: Likewise. * target.h: Likewise. * spellcheck.c: Likewise. * ira-build.c: Likewise. * tree-inline.c: Likewise. * builtins.c: Likewise. * lra-constraints.c: Likewise. * explow.c: Likewise. * hwint.h: Likewise. * targhooks.c: Likewise. * tree-vect-data-refs.c: Likewise. * expr.c: Likewise. * doc/tm.texi: Likewise. * doc/extend.texi: Likewise. * doc/install.texi: Likewise. * doc/md.texi: Likewise. * tree-ssa-tail-merge.c: Likewise. * sched-int.h: Likewise. * match.pd: Likewise. * sched-ebb.c: Likewise. * target.def (omit_struct_return_reg): Likewise. * gimple-ssa-isolate-paths.c: Likewise. (find_implicit_erroneous_behaviour): Renamed to... (find_implicit_erroneous_behavior): ... this. (find_explicit_erroneous_behaviour): Renamed to... (find_explicit_erroneous_behavior): ... this. (gimple_ssa_isolate_erroneous_paths): Adjust caller. gcc/cp/ * error.c: Spelling fixes - behaviour -> behavior and neighbour -> neighbor. * decl.c: Likewise. * typeck.c (cp_build_binary_op): Fix up behavior spelling in diagnostics. * init.c (build_delete): Likewise. gcc/objc/ * objc-act.c: Spelling fixes - behaviour -> behavior and neighbour -> neighbor. * objc-map.h: Likewise. gcc/go/ * gofrontend/lex.cc: Spelling fixes - behaviour -> behavior and neighbour -> neighbor. * gccgo.texi: Likewise. gcc/ada/ * prj-tree.ads: Spelling fixes - behaviour -> behavior and neighbour -> neighbor. * prep.adb: Likewise. * prj.ads: Likewise. * prepcomp.adb: Likewise. * g-socket.ads: Likewise. * s-imgrea.adb: Likewise. * a-calend.adb: Likewise. * exp_disp.adb: Likewise. * doc/gnat_ugn/gnat_utility_programs.rst: Likewise. * g-socket.adb: Likewise. * sem_ch12.adb: Likewise. * terminals.c: Likewise. gcc/testsuite/ * objc.dg/gnu-api-2-method.m: Spelling fixes - behaviour -> behavior and neighbour -> neighbor. * objc.dg/attributes/method-nonnull-1.m: Likewise. * objc.dg/gnu-api-2-class-meta.m: Likewise. * c-c++-common/Wvarargs.c: Likewise. * c-c++-common/goacc/host_data-5.c: Likewise. * obj-c++.dg/gnu-api-2-class-meta.mm: Likewise. * obj-c++.dg/attributes/method-nonnull-1.mm: Likewise. * obj-c++.dg/gnu-api-2-method.mm: Likewise. * gcc.target/aarch64/pr60697.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vldX_lane.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vqshl.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vshuffle.inc: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vrshl.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vldX_dup.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vstX_lane.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vqrshl.c: Likewise. * gcc.target/aarch64/advsimd-intrinsics/vldX.c: Likewise. * gcc.target/aarch64/aapcs64/ice_2.c: Likewise. * gcc.target/aarch64/aapcs64/test_23.c: Likewise. * gcc.target/aarch64/vrnd_f64_1.c: Likewise. * g++.dg/warn/Wconversion-real-integer-3.C: Likewise. * g++.dg/lookup/koenig5.C: Likewise. * g++.dg/ext/no-asm-2.C: Likewise. * gfortran.dg/bounds_check_array_ctor_3.f90: Likewise. * gfortran.dg/bounds_check_array_ctor_7.f90: Likewise. * gfortran.dg/used_types_16.f90: Likewise. * gfortran.dg/assumed_rank_bounds_1.f90: Likewise. * gfortran.dg/bounds_check_array_ctor_1.f90: Likewise. * gfortran.dg/assumed_rank_bounds_2.f90: Likewise. * gfortran.dg/bounds_check_array_ctor_4.f90: Likewise. * gfortran.dg/abstract_type_6.f03: Likewise. * gfortran.dg/bounds_check_array_ctor_5.f90: Likewise. * gfortran.dg/used_types_15.f90: Likewise. * gfortran.dg/bounds_check_array_ctor_8.f90: Likewise. * gfortran.dg/exit_3.f08: Likewise. * gfortran.dg/open_status_2.f90: Likewise. * gfortran.dg/derived_pointer_recursion_2.f90: Likewise. * gfortran.dg/intrinsic_std_1.f90: Likewise. * gfortran.dg/associate_1.f03: Likewise. * gfortran.dg/bounds_check_array_ctor_2.f90: Likewise. * gfortran.dg/intrinsic_std_6.f90: Likewise. * gfortran.dg/bounds_check_array_ctor_6.f90: Likewise. * gcc.dg/builtin-object-size-1.c: Likewise. * gcc.dg/noreturn-6.c: Likewise. * gcc.dg/builtin-stringop-chk-1.c: Likewise. * gcc.dg/globalalias.c: Likewise. * gcc.dg/builtins-config.h: Likewise. * gcc.dg/pr30457.c: Likewise. * gcc.c-torture/compile/volatile-1.c: Likewise. * gcc.c-torture/execute/20101011-1.c: Likewise. * c-c++-common/Waddress-1.c: Likewise. From-SVN: r233358
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/aarch64/aarch64-simd.md2
-rw-r--r--gcc/config/aarch64/aarch64.c4
-rw-r--r--gcc/config/arc/arc.md2
-rw-r--r--gcc/config/arm/arm-c.c2
-rw-r--r--gcc/config/arm/arm.c2
-rw-r--r--gcc/config/arm/cortex-a57.md2
-rw-r--r--gcc/config/arm/neon.md2
-rw-r--r--gcc/config/bfin/bfin.c2
-rw-r--r--gcc/config/cris/cris.opt2
-rw-r--r--gcc/config/i386/i386.c2
-rw-r--r--gcc/config/i386/znver1.md2
-rw-r--r--gcc/config/ia64/hpux-unix2003.h2
-rw-r--r--gcc/config/mips/mips.c4
-rw-r--r--gcc/config/msp430/msp430.md2
-rw-r--r--gcc/config/nvptx/nvptx.c6
-rw-r--r--gcc/config/rs6000/rs6000.c2
-rw-r--r--gcc/config/rx/rx.c2
-rw-r--r--gcc/config/rx/rx.md2
-rw-r--r--gcc/config/s390/s390.c2
-rw-r--r--gcc/config/vms/vms-c.c2
20 files changed, 24 insertions, 24 deletions
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index e1f5682..3047841 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -1785,7 +1785,7 @@
;; the lower architectural lanes of the vector, for these patterns we want
;; to always treat "hi" as referring to the higher architectural lanes.
;; Consequently, while the patterns below look inconsistent with our
-;; other big-endian patterns their behaviour is as required.
+;; other big-endian patterns their behavior is as required.
(define_expand "vec_unpacks_lo_<mode>"
[(match_operand:<VWIDE> 0 "register_operand" "")
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index a2d880d..8326a4c 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -8632,14 +8632,14 @@ enum aarch64_attr_opt_type
/* All the information needed to handle a target attribute.
NAME is the name of the attribute.
- ATTR_TYPE specifies the type of behaviour of the attribute as described
+ ATTR_TYPE specifies the type of behavior of the attribute as described
in the definition of enum aarch64_attr_opt_type.
ALLOW_NEG is true if the attribute supports a "no-" form.
HANDLER is the function that takes the attribute string and whether
it is a pragma or attribute and handles the option. It is needed only
when the ATTR_TYPE is aarch64_attr_custom.
OPT_NUM is the enum specifying the option that the attribute modifies.
- This is needed for attributes that mirror the behaviour of a command-line
+ This is needed for attributes that mirror the behavior of a command-line
option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
aarch64_attr_enum. */
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 602cf0b..6a8ec83 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -4721,7 +4721,7 @@
;; Comment in final.c (insn_current_reference_address) says
;; forward branch addresses are calculated from the next insn after branch
;; and for backward branches, it is calculated from the branch insn start.
- ;; The shortening logic here is tuned to accomodate this behaviour
+ ;; The shortening logic here is tuned to accomodate this behavior
;; ??? This should be grokked by the ccfsm machinery.
(define_insn "cbranchsi4_scratch"
[(set (pc)
diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c
index 2f1035b..982a606 100644
--- a/gcc/config/arm/arm-c.c
+++ b/gcc/config/arm/arm-c.c
@@ -164,7 +164,7 @@ arm_cpu_builtins (struct cpp_reader* pfile)
if (arm_arch_iwmmxt2)
builtin_define ("__IWMMXT2__");
/* ARMv6KZ was originally identified as the misspelled __ARM_ARCH_6ZK__. To
- preserve the existing behaviour, the misspelled feature macro must still be
+ preserve the existing behavior, the misspelled feature macro must still be
defined. */
if (arm_arch6kz)
builtin_define ("__ARM_ARCH_6ZK__");
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 82becef..6b73771 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -28899,7 +28899,7 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in,
shift-by-register would give. This helps reduce execution
differences between optimization levels, but it won't stop other
parts of the compiler doing different things. This is "undefined
- behaviour, in any case. */
+ behavior, in any case. */
if (INTVAL (amount) <= 0)
emit_insn (gen_movdi (out, in));
else if (INTVAL (amount) >= 64)
diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
index 758d382..ca6cfc0 100644
--- a/gcc/config/arm/cortex-a57.md
+++ b/gcc/config/arm/cortex-a57.md
@@ -324,7 +324,7 @@
"ca57_mx")
;; All multiplies
-;; TODO: AArch32 and AArch64 have different behaviour
+;; TODO: AArch32 and AArch64 have different behavior
(define_insn_reservation "cortex_a57_mult32" 3
(and (eq_attr "tune" "cortexa57")
(ior (eq_attr "mul32" "yes")
diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index f495d40..879c07c 100644
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -1836,7 +1836,7 @@
; particular, denormal values are flushed to zero. This means that GCC cannot
; use those instructions for autovectorization, etc. unless
; -funsafe-math-optimizations is in effect (in which case flush-to-zero
-; behaviour is permissible). Intrinsic operations (provided by the arm_neon.h
+; behavior is permissible). Intrinsic operations (provided by the arm_neon.h
; header) must work in either case: if -funsafe-math-optimizations is given,
; intrinsics expand to "canonical" RTL where possible, otherwise intrinsics
; expand to unspecs (which may potentially limit the extent to which they might
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index 120cd79..75ddcf0 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -4092,7 +4092,7 @@ reorder_var_tracking_notes (void)
}
/* On some silicon revisions, functions shorter than a certain number of cycles
- can cause unpredictable behaviour. Work around this by adding NOPs as
+ can cause unpredictable behavior. Work around this by adding NOPs as
needed. */
static void
workaround_rts_anomaly (void)
diff --git a/gcc/config/cris/cris.opt b/gcc/config/cris/cris.opt
index 918c824..1b663eb 100644
--- a/gcc/config/cris/cris.opt
+++ b/gcc/config/cris/cris.opt
@@ -21,7 +21,7 @@
; TARGET_MUL_BUG: Whether or not to work around multiplication
; instruction hardware bug when generating code for models where
; it may be present. From the trouble report for Etrax 100 LX:
-; "A multiply operation may cause incorrect cache behaviour
+; "A multiply operation may cause incorrect cache behavior
; under some specific circumstances. The problem can occur if
; the instruction following the multiply instruction causes a
; cache miss, and multiply operand 1 (source operand) bits
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 1215ae4..a1c87ab 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -19705,7 +19705,7 @@ distance_non_agu_define_in_bb (unsigned int regno1, unsigned int regno2,
/* Search backward for non-agu definition of register number REGNO1
or register number REGNO2 in INSN's basic block until
1. Pass LEA_SEARCH_THRESHOLD instructions, or
- 2. Reach neighbour BBs boundary, or
+ 2. Reach neighbor BBs boundary, or
3. Reach agu definition.
Returns the distance between the non-agu definition point and INSN.
If no definition point, returns -1. */
diff --git a/gcc/config/i386/znver1.md b/gcc/config/i386/znver1.md
index b7fcf6c..6e23188 100644
--- a/gcc/config/i386/znver1.md
+++ b/gcc/config/i386/znver1.md
@@ -40,7 +40,7 @@
;; Direct instructions can be issued to any of the four decoders.
(define_reservation "znver1-direct" "znver1-decode0|znver1-decode1|znver1-decode2|znver1-decode3")
-;; Fix me: Need to revisit this later to simulate fast path double behaviour.
+;; Fix me: Need to revisit this later to simulate fast path double behavior.
(define_reservation "znver1-double" "znver1-direct")
diff --git a/gcc/config/ia64/hpux-unix2003.h b/gcc/config/ia64/hpux-unix2003.h
index 36418be..0997723 100644
--- a/gcc/config/ia64/hpux-unix2003.h
+++ b/gcc/config/ia64/hpux-unix2003.h
@@ -1,6 +1,6 @@
/* For HP-UX 11.31 and greater, use unix2003.o instead of unix98.o to
- get correct C99 snprintf behaviour with buffer overflow. */
+ get correct C99 snprintf behavior with buffer overflow. */
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "%{!shared:%{static:crt0%O%s} \
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 697abc2..5af3d1e 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -13519,7 +13519,7 @@ mips_process_sync_loop (rtx_insn *insn, rtx *operands)
/* When using branch likely (-mfix-r10000), the delay slot instruction
will be annulled on false. The normal delay slot instructions
calculate the overall result of the atomic operation and must not
- be annulled. To ensure this behaviour unconditionally use a NOP
+ be annulled. To ensure this behavior unconditionally use a NOP
in the delay slot for the branch likely case. */
if (TARGET_CB_MAYBE)
@@ -19121,7 +19121,7 @@ void mips_function_profiler (FILE *file)
}
/* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the default
- behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
+ behavior of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even
when TARGET_LOONGSON_VECTORS is true. */
static unsigned HOST_WIDE_INT
diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md
index bcf5dac..4df4970 100644
--- a/gcc/config/msp430/msp430.md
+++ b/gcc/config/msp430/msp430.md
@@ -738,7 +738,7 @@
;;
;; Note - we ignore shift counts of less than one or more than 15.
;; This is permitted by the ISO C99 standard as such shifts result
-;; in "undefined" behaviour. [6.5.7 (3)]
+;; in "undefined" behavior. [6.5.7 (3)]
;; signed A << C
diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c
index 78614f8..a955c04 100644
--- a/gcc/config/nvptx/nvptx.c
+++ b/gcc/config/nvptx/nvptx.c
@@ -600,7 +600,7 @@ write_arg_mode (std::stringstream &s, int for_reg, int argno,
is true, if this is a prototyped function, rather than an old-style
C declaration. Returns the next argument number to use.
- The promotion behaviour here must match the regular GCC function
+ The promotion behavior here must match the regular GCC function
parameter marshalling machinery. */
static int
@@ -652,7 +652,7 @@ write_return_mode (std::stringstream &s, bool for_proto, machine_mode mode)
/* Process a function return TYPE to emit a PTX return as a prototype
or function prologue declaration. Returns true if return is via an
- additional pointer parameter. The promotion behaviour here must
+ additional pointer parameter. The promotion behavior here must
match the regular GCC function return mashalling. */
static bool
@@ -1620,7 +1620,7 @@ nvptx_assemble_decl_begin (FILE *file, const char *name, const char *section,
elt_size &= -elt_size; /* Extract LSB set. */
init_frag.size = elt_size;
- /* Avoid undefined shift behaviour by using '2'. */
+ /* Avoid undefined shift behavior by using '2'. */
init_frag.mask = ((unsigned HOST_WIDE_INT)2
<< (elt_size * BITS_PER_UNIT - 1)) - 1;
init_frag.val = 0;
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index c7e0634..eed50f4 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -26060,7 +26060,7 @@ rs6000_emit_prologue (void)
because code emitted by gcc for a (non-pointer) function call
doesn't save and restore R2. Instead, R2 is managed out-of-line
by a linker generated plt call stub when the function resides in
- a shared library. This behaviour is costly to describe in DWARF,
+ a shared library. This behavior is costly to describe in DWARF,
both in terms of the size of DWARF info and the time taken in the
unwinder to interpret it. R2 changes, apart from the
calls_eh_return case earlier in this function, are handled by
diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index 4cf840c..88cf18c 100644
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -2884,7 +2884,7 @@ rx_file_start (void)
static bool
rx_is_ms_bitfield_layout (const_tree record_type ATTRIBUTE_UNUSED)
{
- /* The packed attribute overrides the MS behaviour. */
+ /* The packed attribute overrides the MS behavior. */
return ! TYPE_PACKED (record_type);
}
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index 5b79e6a..787c37b 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -408,7 +408,7 @@
;; Note - the following set of patterns do not use the "memory_operand"
;; predicate or an "m" constraint because we do not allow symbol_refs
;; or label_refs as legitimate memory addresses. This matches the
-;; behaviour of most of the RX instructions. Only the call/branch
+;; behavior of most of the RX instructions. Only the call/branch
;; instructions are allowed to refer to symbols/labels directly.
;; The call operands are in QImode because that is the value of
;; FUNCTION_MODE
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 299d9a8..9facd96 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -13603,7 +13603,7 @@ s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
The loop is analyzed for memory accesses by calling check_dpu for
each rtx of the loop. Depending on the loop_depth and the amount of
memory accesses a new number <=nunroll is returned to improve the
- behaviour of the hardware prefetch unit. */
+ behavior of the hardware prefetch unit. */
static unsigned
s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
{
diff --git a/gcc/config/vms/vms-c.c b/gcc/config/vms/vms-c.c
index f2f5199..392b2db 100644
--- a/gcc/config/vms/vms-c.c
+++ b/gcc/config/vms/vms-c.c
@@ -151,7 +151,7 @@ vms_pragma_nomember_alignment (cpp_reader *pfile ATTRIBUTE_UNUSED)
1) extern int name;
2) int name;
3) int name = 5;
- See below for the behaviour as implemented by the native compiler.
+ See below for the behavior as implemented by the native compiler.
*/
enum extern_model_kind