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| author | Tejas Belagod <tejas.belagod@arm.com> | 2022-12-15 07:57:50 +0000 |
|---|---|---|
| committer | Tejas Belagod <tejas.belagod@arm.com> | 2023-01-20 09:43:24 +0000 |
| commit | 99ea0d7611605d2d1a67a6021cb78f0bdd5c609b (patch) | |
| tree | 6e3379f80a96a2c9a6fced62ec56bd4d656ac16a /gcc/config | |
| parent | 16bd9e14f226e07bf0ffb9d68084c9ad69bf7b45 (diff) | |
| download | gcc-99ea0d7611605d2d1a67a6021cb78f0bdd5c609b.zip gcc-99ea0d7611605d2d1a67a6021cb78f0bdd5c609b.tar.gz gcc-99ea0d7611605d2d1a67a6021cb78f0bdd5c609b.tar.bz2 | |
AArch64: Gate various crypto intrinsics availability based on features
The 64-bit variant of PMULL{2} and AES instructions are available if FEAT_AES
is implemented according to the Arm ARM [1]. Similarly FEAT_SHA1 and
FEAT_SHA256 enable the use of SHA1 and SHA256 instruction variants.
This patch fixes arm_neon.h to correctly reflect the feature availability based
on '+aes' and '+sha2' as opposed to the ambiguous catch-all '+crypto'.
[1] Section D17.2.61, C7.2.215
2022-01-11 Tejas Belagod <tejas.belagod@arm.com>
gcc/ChangeLog:
* config/aarch64/arm_neon.h (vmull_p64, vmull_high_p64, vaeseq_u8,
vaesdq_u8, vaesmcq_u8, vaesimcq_u8): Gate under "nothing+aes".
(vsha1*_u32, vsha256*_u32): Gate under "nothing+sha2".
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/acle/pmull64.c: New.
* gcc.target/aarch64/aes-fuse-1.c: Replace '+crypto' with corresponding
feature flag based on the intrinsic.
* gcc.target/aarch64/aes-fuse-2.c: Likewise.
* gcc.target/aarch64/aes_1.c: Likewise.
* gcc.target/aarch64/aes_2.c: Likewise.
* gcc.target/aarch64/aes_xor_combine.c: Likewise.
* gcc.target/aarch64/sha1_1.c: Likewise.
* gcc.target/aarch64/sha256_1.c: Likewise.
* gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/aarch64/arm_neon.h | 35 |
1 files changed, 18 insertions, 17 deletions
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index cdc2b63..eeec9f1 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -7496,7 +7496,7 @@ vqrdmlshs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d) #pragma GCC pop_options #pragma GCC push_options -#pragma GCC target ("+nothing+crypto") +#pragma GCC target ("+nothing+aes") /* vaes */ __extension__ extern __inline uint8x16_t @@ -7526,6 +7526,22 @@ vaesimcq_u8 (uint8x16_t data) { return __builtin_aarch64_crypto_aesimcv16qi_uu (data); } + +__extension__ extern __inline poly128_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_p64 (poly64_t __a, poly64_t __b) +{ + return + __builtin_aarch64_crypto_pmulldi_ppp (__a, __b); +} + +__extension__ extern __inline poly128_t +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vmull_high_p64 (poly64x2_t __a, poly64x2_t __b) +{ + return __builtin_aarch64_crypto_pmullv2di_ppp (__a, __b); +} + #pragma GCC pop_options /* vcage */ @@ -20772,7 +20788,7 @@ vrsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c) } #pragma GCC push_options -#pragma GCC target ("+nothing+crypto") +#pragma GCC target ("+nothing+sha2") /* vsha1 */ @@ -20849,21 +20865,6 @@ vsha256su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w8_11, uint32x4_t __w12_15) __w12_15); } -__extension__ extern __inline poly128_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmull_p64 (poly64_t __a, poly64_t __b) -{ - return - __builtin_aarch64_crypto_pmulldi_ppp (__a, __b); -} - -__extension__ extern __inline poly128_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -vmull_high_p64 (poly64x2_t __a, poly64x2_t __b) -{ - return __builtin_aarch64_crypto_pmullv2di_ppp (__a, __b); -} - #pragma GCC pop_options /* vshl */ |