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| author | Roger Sayle <roger@nextmovesoftware.com> | 2022-01-21 18:42:30 +0000 |
|---|---|---|
| committer | Roger Sayle <roger@nextmovesoftware.com> | 2022-01-21 18:50:22 +0000 |
| commit | 886e9779581102caf97cd05dea80d9be87c24784 (patch) | |
| tree | dbc28f07650d7c1ea9d7faf1ce95dffb1e5b230c /gcc/config | |
| parent | 85419ac59724b7ce710ebb4acf03dbd747edeea3 (diff) | |
| download | gcc-886e9779581102caf97cd05dea80d9be87c24784.zip gcc-886e9779581102caf97cd05dea80d9be87c24784.tar.gz gcc-886e9779581102caf97cd05dea80d9be87c24784.tar.bz2 | |
PR middle-end/104140: bootstrap ICE on riscv.
This patch resolves the P1 "ice-on-valid-code" regression boostrapping
GCC on risv-unknown-linux-gnu caused by my recent MULT_HIGHPART_EXPR
functionality. RISC-V differs from x86_64 and many targets by
supporting a usmusidi3 instruction, basically a widening multiply
where one operand is signed and the other is unsigned. Alas the
final version of my patch to recognize MULT_HIGHPART_EXPR didn't
sufficiently defend against the operands of WIDEN_MULT_EXPR having
different signedness. This is fixed by the two-line change to
tree-ssa-math-opts.cc's convert_mult_to_highpart in the patch below.
The majority of the rest of the patch is to the documentation
(in tree.def and generic.texi). It turns out that WIDEN_MULT_EXPR
wasn't previously documented in generic.texi, let alone the slightly
unusual semantics of allowing mismatched (signed vs unsigned) operands.
This also clarifies that MULT_HIGHPART_EXPR currently requires the
signedness of operands to match [but this might change in a future
release of GCC to support targets with usmul<mode>3_highpart].
The one final chunk of this patch (that is hopefully sufficiently
close to obvious for stage 4) is a similar (NULL pointer) sanity
check in riscv_cpu_cpp_builtins. Currently running cc1 from the
command line (or from gdb) without specifying -march results in a
segmentation fault (ICE). This is a minor annoyance tracking down
issues (in cross compilers) for riscv, and trivially fixed as below.
2022-01-22 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR middle-end/104140
* tree-ssa-math-opts.cc (convert_mult_to_highpart): Check that the
operands of the widening multiplication are either both signed or
both unsigned, and abort the conversion if mismatched.
* doc/generic.texi (WIDEN_MULT_EXPR): Describe expression node.
(MULT_HIGHPART_EXPR): Clarify that operands must have the same
signedness.
* tree.def (MULT_HIGHPART_EXPR): Document both operands must have
integer types with the same precision and signedness.
(WIDEN_MULT_EXPR): Document that operands must have integer types
with the same precision, but possibly differing signedness.
* config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Defend against
riscv_current_subset_list returning a NULL pointer (empty list).
gcc/testsuite/ChangeLog
PR middle-end/104140
* gcc.target/riscv/pr104140.c: New test case.
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/riscv/riscv-c.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 211472f..73c62f4 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -108,6 +108,9 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) builtin_define_with_int_value ("__riscv_arch_test", 1); const riscv_subset_list *subset_list = riscv_current_subset_list (); + if (!subset_list) + return; + size_t max_ext_len = 0; /* Figure out the max length of extension name for reserving buffer. */ |