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| author | Uros Bizjak <ubizjak@gmail.com> | 2016-12-02 19:48:35 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2016-12-02 19:48:35 +0100 |
| commit | 81cff75ff9178e9344e1f4c8935ffd451f66632f (patch) | |
| tree | 4780cc081d7634ec454df427b6fc429ef28d29e9 /gcc/config | |
| parent | 6ed022af2addc38c0d7c2b321d279a48f73f11c4 (diff) | |
| download | gcc-81cff75ff9178e9344e1f4c8935ffd451f66632f.zip gcc-81cff75ff9178e9344e1f4c8935ffd451f66632f.tar.gz gcc-81cff75ff9178e9344e1f4c8935ffd451f66632f.tar.bz2 | |
re PR target/70322 (STV doesn't optimize andn)
PR target/70322
* config/i386/i386.md (*andndi3_doubleword): Add non-BMI alternative
and corresponding post-reload splitter.
testsuite/ChangeLog:
PR target/70322
* gcc.target/i386/pr70322-2.c (dg-final): Remove xfail.
From-SVN: r243202
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/i386.md | 51 |
1 files changed, 39 insertions, 12 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index da7cb07..773f29b 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -8534,15 +8534,24 @@ operands[2] = gen_lowpart (QImode, operands[2]); }) -(define_insn_and_split "*andndi3_doubleword" - [(set (match_operand:DI 0 "register_operand" "=r") +(define_insn "*andndi3_doubleword" + [(set (match_operand:DI 0 "register_operand" "=r,&r") (and:DI - (not:DI (match_operand:DI 1 "register_operand" "r")) - (match_operand:DI 2 "nonimmediate_operand" "rm"))) + (not:DI (match_operand:DI 1 "register_operand" "r,0")) + (match_operand:DI 2 "nonimmediate_operand" "rm,rm"))) (clobber (reg:CC FLAGS_REG))] - "TARGET_BMI && !TARGET_64BIT && TARGET_STV && TARGET_SSE2" + "!TARGET_64BIT && TARGET_STV && TARGET_SSE2" "#" - "&& reload_completed" + [(set_attr "isa" "bmi,*")]) + +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI + (not:DI (match_operand:DI 1 "register_operand")) + (match_operand:DI 2 "nonimmediate_operand"))) + (clobber (reg:CC FLAGS_REG))] + "!TARGET_64BIT && TARGET_BMI && TARGET_STV && TARGET_SSE2 + && reload_completed" [(parallel [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2))) (clobber (reg:CC FLAGS_REG))]) @@ -8551,6 +8560,24 @@ (clobber (reg:CC FLAGS_REG))])] "split_double_mode (DImode, &operands[0], 3, &operands[0], &operands[3]);") +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI + (not:DI (match_dup 0)) + (match_operand:DI 1 "nonimmediate_operand"))) + (clobber (reg:CC FLAGS_REG))] + "!TARGET_64BIT && !TARGET_BMI && TARGET_STV && TARGET_SSE2 + && reload_completed" + [(set (match_dup 0) (not:SI (match_dup 0))) + (parallel [(set (match_dup 0) + (and:SI (match_dup 0) (match_dup 1))) + (clobber (reg:CC FLAGS_REG))]) + (set (match_dup 2) (not:SI (match_dup 2))) + (parallel [(set (match_dup 2) + (and:SI (match_dup 2) (match_dup 3))) + (clobber (reg:CC FLAGS_REG))])] + "split_double_mode (DImode, &operands[0], 2, &operands[0], &operands[2]);") + (define_insn "*andn<mode>_1" [(set (match_operand:SWI48 0 "register_operand" "=r,r") (and:SWI48 @@ -9312,6 +9339,12 @@ ;; One complement instructions +(define_expand "one_cmpl<mode>2" + [(set (match_operand:SWIM1248x 0 "nonimmediate_operand") + (not:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand")))] + "" + "ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;") + (define_insn_and_split "*one_cmpldi2_doubleword" [(set (match_operand:DI 0 "nonimmediate_operand" "=rm") (not:DI (match_operand:DI 1 "nonimmediate_operand" "0")))] @@ -9325,12 +9358,6 @@ (not:SI (match_dup 3)))] "split_double_mode (DImode, &operands[0], 2, &operands[0], &operands[2]);") -(define_expand "one_cmpl<mode>2" - [(set (match_operand:SWIM1248x 0 "nonimmediate_operand") - (not:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand")))] - "" - "ix86_expand_unary_operator (NOT, <MODE>mode, operands); DONE;") - (define_insn "*one_cmpl<mode>2_1" [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm") (not:SWI248 (match_operand:SWI248 1 "nonimmediate_operand" "0")))] |