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authorEric Christopher <echristo@gcc.gnu.org>2002-04-10 03:40:00 +0000
committerEric Christopher <echristo@gcc.gnu.org>2002-04-10 03:40:00 +0000
commit7b2e1077614049c9899772aa14edab91e80e7ec5 (patch)
tree0ec004e3c4961b9c4fda3c7a8bc66bd90915255f /gcc/config
parentef98ad7b6c7497649c066ec2be0a44f340038dda (diff)
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mips.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Add additional information to .comm directive.
2002-04-09 Eric Christopher <echristo@redhat.com> * config/mips/mips.h (ASM_OUTPUT_ALIGNED_DECL_COMMON): Add additional information to .comm directive. From-SVN: r52109
Diffstat (limited to 'gcc/config')
-rw-r--r--gcc/config/mips/mips.h9
1 files changed, 6 insertions, 3 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 976f0b7..6db24f4 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -2311,7 +2311,7 @@ extern enum reg_class mips_char_to_class[256];
memory and loading that memory location into a register of CLASS2.
Do not define this macro if its value would always be zero. */
-
+#if 0
#define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
((!TARGET_DEBUG_H_MODE \
&& GET_MODE_CLASS (MODE) == MODE_INT \
@@ -2320,7 +2320,7 @@ extern enum reg_class mips_char_to_class[256];
|| (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
&& ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
|| (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
-
+#endif
/* The HI and LO registers can only be reloaded via the general
registers. Condition code registers can only be loaded to the
general registers, and from the floating point registers. */
@@ -4485,8 +4485,11 @@ while (0)
(SIZE)); \
} \
else \
- mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
+ { \
+ mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u", \
(SIZE)); \
+ fprintf ((STREAM), "%u\n", ((unsigned)(ALIGN) / BITS_PER_UNIT));\
+ } \
} while (0)