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| author | Kaz Kojima <kkojima@gcc.gnu.org> | 2014-12-19 04:53:57 +0000 |
|---|---|---|
| committer | Kaz Kojima <kkojima@gcc.gnu.org> | 2014-12-19 04:53:57 +0000 |
| commit | 74bd0da1fd3bdffc036f0449c4d3ea7c95129585 (patch) | |
| tree | 33cd90625d58ad0a3f152bce4b67b197a0386ad3 /gcc/config | |
| parent | 6efc6b7f05d7ea5bae0fb18dd2c8cec4aa69eb48 (diff) | |
| download | gcc-74bd0da1fd3bdffc036f0449c4d3ea7c95129585.zip gcc-74bd0da1fd3bdffc036f0449c4d3ea7c95129585.tar.gz gcc-74bd0da1fd3bdffc036f0449c4d3ea7c95129585.tar.bz2 | |
* [SH] Add splitter to addsi3_compact.
From-SVN: r218891
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/sh/predicates.md | 13 | ||||
| -rw-r--r-- | gcc/config/sh/sh.md | 29 |
2 files changed, 35 insertions, 7 deletions
diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md index 152056a..8772332 100644 --- a/gcc/config/sh/predicates.md +++ b/gcc/config/sh/predicates.md @@ -182,6 +182,19 @@ return 0; }) +;; Likewise arith_operand but always permits const_int. +(define_predicate "arith_or_int_operand" + (match_code "subreg,reg,const_int,const_vector") +{ + if (arith_operand (op, mode)) + return 1; + + if (CONST_INT_P (op)) + return 1; + + return 0; +}) + ;; Returns 1 if OP is a valid source operand for a compare insn. (define_predicate "arith_reg_or_0_operand" (match_code "subreg,reg,const_int,const_vector") diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md index 76f5c4a..a74e17f 100644 --- a/gcc/config/sh/sh.md +++ b/gcc/config/sh/sh.md @@ -2020,11 +2020,16 @@ (define_expand "addsi3" [(set (match_operand:SI 0 "arith_reg_operand" "") (plus:SI (match_operand:SI 1 "arith_operand" "") - (match_operand:SI 2 "arith_operand" "")))] + (match_operand:SI 2 "arith_or_int_operand" "")))] "" { if (TARGET_SHMEDIA) operands[1] = force_reg (SImode, operands[1]); + else if (! arith_operand (operands[2], SImode)) + { + if (reg_overlap_mentioned_p (operands[0], operands[1])) + FAIL; + } }) (define_insn "addsi3_media" @@ -2051,12 +2056,22 @@ [(set_attr "type" "arith_media") (set_attr "highpart" "ignore")]) -(define_insn "*addsi3_compact" - [(set (match_operand:SI 0 "arith_reg_dest" "=r") - (plus:SI (match_operand:SI 1 "arith_operand" "%0") - (match_operand:SI 2 "arith_operand" "rI08")))] - "TARGET_SH1" - "add %2,%0" +(define_insn_and_split "*addsi3_compact" + [(set (match_operand:SI 0 "arith_reg_dest" "=r,&r") + (plus:SI (match_operand:SI 1 "arith_operand" "%0,r") + (match_operand:SI 2 "arith_or_int_operand" "rI08,rn")))] + "TARGET_SH1 + && (rtx_equal_p (operands[0], operands[1]) + && arith_operand (operands[2], SImode)) + || ! reg_overlap_mentioned_p (operands[0], operands[1])" + "@ + add %2,%0 + #" + "reload_completed + && ! reg_overlap_mentioned_p (operands[0], operands[1])" + [(set (match_dup 0) (match_dup 2)) + (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))] + "" [(set_attr "type" "arith")]) ;; ------------------------------------------------------------------------- |