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| author | Jan Hubicka <hubicka@ucw.cz> | 2017-11-02 14:49:31 +0100 |
|---|---|---|
| committer | Jan Hubicka <hubicka@gcc.gnu.org> | 2017-11-02 13:49:31 +0000 |
| commit | 6d7e169ebd50ff5c2ba8f251877ed5a2fb489a2d (patch) | |
| tree | 346c4bc4a24fc9f6b97513a142e440fa8c515426 /gcc/config | |
| parent | 1e8fc1ce6e1747ffffa46f7e796640feb782572a (diff) | |
| download | gcc-6d7e169ebd50ff5c2ba8f251877ed5a2fb489a2d.zip gcc-6d7e169ebd50ff5c2ba8f251877ed5a2fb489a2d.tar.gz gcc-6d7e169ebd50ff5c2ba8f251877ed5a2fb489a2d.tar.bz2 | |
* x86-tune.def (X86_TUNE_USE_INCDEC): Enable for Haswell+.
From-SVN: r254343
Diffstat (limited to 'gcc/config')
| -rw-r--r-- | gcc/config/i386/x86-tune.def | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index c7099d7..99282c8 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -220,10 +220,15 @@ DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_GENERIC) as "add mem, reg". */ DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO)) -/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions. */ +/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions. + + Core2 and nehalem has stall of 7 cycles for partial flag register stalls. + Sandy bridge and Ivy bridge generate extra uop. On Haswell this extra uop + is output only when the values needs to be really merged, which is not + done by GCC generated code. */ DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec", - ~(m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL - | m_KNL | m_KNM | m_GENERIC)) + ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE + | m_BONNELL | m_SILVERMONT | m_INTEL | m_KNL | m_KNM | m_GENERIC)) /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred for DFmode copies */ |